Where to find Information about Virtualization in RISC-V?


The latest Draft for the Priviledged ISA Specification on riscv.org is version 1.10. The draft is now a little over a year old. My issue is there is only a place holder for Chapter 5: Hypervisor Extensions, Version 0.0.
In addition, I looked at the public documents from the RISC-V: Privileged Spec working group. However, this is pretty much empty as well.

My question is where can I find more information about virtualization and hypervisor in RISC-V? I am particularly interested in the following topics:

  • Bare-metal (type-1) hypervisor support in RISC-V.
  • Hosted (type-2) hypervisor support in RISC-V.
  • Second Level Address Translation (SLAT) in RISC-V.
  • IOMMU (Input/Output Memory Management Unit) in RISC-V.
  • Virtualization support for peripherals (GPU etc.) support in RISC-V.
  • Recursive (a.k.a nested) virtualization support.
  • Is there currently any team working on porting their hypversior to RISC-V?

(Megan A. Wachs) #2

You could take a look at the riscv-isa-manual github, which is where you can see the Work-in-Progress drafts:

(Jim Wilson) #3

There was a presentation at the November 2017 RISC-V workshop.

It points at the github riscv-isa-manual also.


Does someone have any idea on when the draft for the virtualization extensions will be finished? Also, I’d love to know about some team working on hypervisors for RISC-V or some test implementation of the current state of the specs…


I would also be interested to know the current state of the specs.