RISC-V Privileged Architecture draft v1.9 released

I’m happy to announce that, in collaboration with our friends at UC Berkeley, we’ve converged on a new draft specification of the RISC-V privileged architecture. The release of this draft spec is a significant milestone: the design space is far larger than that of the user ISA, and to arrive at what we think is an elegant solution was an undertaking of many late nights and innumerable pints.

In RISC-V land, we use v2.0 to signify that a spec has been frozen, and v1.9 to signify a spec that we intend to freeze, barring good reason not to. So, after a round of feedback from the RISC-V community, we expect to propose something very similar to v1.9 as the standard privilege architecture.

The spec is available at the RISC-V Foundation web site: https://riscv.org/specifications/privileged-isa/. Notable features since the last version include a standardized platform-level interrupt controller; simpler exception handling; a virtual memory scheme that allows execute-only paging; and an outline of a standard way of describing the hardware platform to the low-level software.