The official design RISC-V architecture


(Nhan Le) #1

Hello everyone!
I’m Nhan. I’m studying Computer Architecture subject at my university. In this subject, I was introduced the RISC-V architecture by my professor and having a project subject to design again and implement this design. My team had done the design completely. We’re searching for some official completely design for comparing. Furthermore, we want to find some tools or orthodox testing methods, which have been accepted by the RISC-V foundation, for this comparison. Above all, all data in our paper need to be compare with orthodox design or announcement. Can you help us get the official design or some tools to complete the benchmark? Thank you very much!
Nhan Le.


(Jim Wilson) #2

The spike simulator, which is in the github.com/riscv/riscv-isa-sim repo is generally accepted as the golden standard for the architecture. There is no official standard hardware design. You can find a list of cores from various sources with various features at riscv.org/risc-v-cores/ Some of these are free, and some of them can be compiled to run on fpga boards, or work with verilog simulators, etc. rocket is the original one out of UC Berkeley.

There are some tests that can be found in github.com/riscv/riscv-tests which are low level tests useful for validating an initial hardware design. I believe that there is a task group that is working on some official testsuite for validating cores that claim to support the RISC-V ISA, but I don’t know anything about it, and don’t know if they have anything useful yet.

The github.com/riscv/riscv-tools repo includes both riscv-isa-sim and riscv-tests and also some other tools useful to hardware designers. Unfortunately it is poorly maintained and difficult to build.