What are the step-by-step instructions to get Spike RISC-V simulator setup for Freedom Studio? I am unsure how to run the code after building a hello-world project from the samples.
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I have no idea about Freedom Studio as I’ve never used it, but here’s how to get 32 bit spike working
sudo apt-get install device-tree-compiler
mkdir temp
cd temp
mkdir _install
export PATH=`pwd`/_install/bin:$PATH
git clone https://github.com/riscv/riscv-isa-sim.git
pushd riscv-isa-sim
mkdir build
cd build
../configure --prefix=`pwd`/../../_install --with-isa=RV32IMAC
make -j`nproc`
make install
popd
git clone https://github.com/riscv/riscv-pk.git
pushd riscv-pk
mkdir build
cd build
../configure --prefix=`pwd`/../../_install --host=riscv64-unknown-elf --with-arch=rv32imac
make -j`nproc`
make install
popd
There is one more non-obvious step, which I think indicates a bug in pk’s build system:
ln -s riscv32-unknown-elf _install/riscv64-unknown-elf
You can now run riscv32 programs using spike.
For programs that use the POSIX library:
spike pk myProgram
For programs that run on bare metal:
spike myProgram
e.g.
$ riscv64-unknown-elf-gcc ~/programs/hello.c -o hello -march=rv32imac -mabi=ilp32
$ spike pk hello
bbl loader
Hello World!
$Thank you, @bruce! However, do you know anyone in SiFive that can answer my query about Freedom Studio? I would like to figure out how to configure the spike simulator to run the hello-world.c program inside the Eclipse-based IDE.
Good to hear that you are using our Freedom Studio IDE.
Can you tell a bit about your reasons for wanting to run your code on Spike.
Have you tried to run it on QEMU that is already bundled as part of Freedom Studio?
I would like to simulate a RISC-V SiFive processor in spike. Does QEMU do that too with high fidelity? Please let me know if you can help ASAP because I would like to play with this functionality.
Not sure what you mean by “high fidelity”.
QEMU is a system emulator and not an ISA simulator like Spike, but for running RISC-V software without HW it’s pretty good.
We do not have Spike integrated in Freedom Studio, only QEMU is integrated in Freedom Studio.
So if you want to go with Spike, you need to run it from command line like @bruce suggested.
@cgsfv : What are the step-by-step instructions to set up QEMU inside Freedom Studio for simulating RISC-V SiFive chip?
QEMU is already bundled with Freedom Studio, so you simply create a New “Freedom E SDK Software Project” and select one of the “qemu-…” targets and select one of the examples programs and you should be good to go.
Qemu does not simulate any specific RISC-V CPU. Its aim is to run generic RISC-V code as quickly as possible (at least portably possible) by JITing the RISC-V code to x86, ARM or whatever. Qemu can use the memory map and peripherals of a few specific boards, including SiFive boards, but the CPU emulation is generic. Typical execution speed is around 1 GIPS.
Spike is a simple interpreter of RISC-V code, designed to be obviously correct and easy to extend rather than to be fast. Again, Spike does not simulate any specific RISC-V CPU. Spike is maybe 10x slower than Qemu (around 100 MIPS), making it less useful for generic software development. However it can produce detailed instruction by instruction logs of execution, including machine-readable output of what register(s) is modified with what new value by each instruction. Spike does not in general provide peripherals, but just a CPU and RAM emulation, with a communication channel. It is used for example by hardware designers to execute in lockstep with simulation of new CPU cores to check they produce correct program flow and results.
If you want high fidelity simulation of a specific RISC-V core then you need the actual RTL for that core, and run it either in a software simulator such as Verilator (at 10s of KIPS) or in an FPGA (typically at 30 to 100 MIPS).
Thank you, @bruce, for your lengthy explanation and response! I really appreciate it. This will really help me with my work. However, isn’t the RISC-V not FPGA or have to do anything with FPGA? Something is wrong here. Please check out the following list of chips following the RISC-V: https://github.com/riscv/riscv-cores-list. They are SoC and Cores; none of which say FPGA.
The RTL for any core can be implemented in either an FPGA or in a custom chip.
Making a custom chip costs maybe from $100k to a few million dollars (and a few months) every time you want to change something. But they run fast (up to 1 or 2 GHz)
Programming an FPGA is free once you own the FPGA board, and takes a few minutes to an hour or two, but runs at typically only 30 to 100 MHz.
A number of cores in the list you point to are primarily used in FPGAs, and probably never have been made in a custom chip (but they could be). These include VexRiscv, ReonV. PicoRV32, SERV, Tinyriscv and probably most of the other ones I’ve never heard of that say “github” and/or have a human name next to them rather than a company.
Conversely, all companies test their cores in FPGA (or similar) before they make a custom chip.
Thank you, Shyamal Chandra, for sharing!
I want to know, that how can I run some custom C code, instead of using those examples already given by the Freedom Studio.
Did you found it ?
I try myself but I was not able to compile a simple “Hello World” in C with risc-v simulator.
I did just try the instruction above, and after the second make -jnproc
I get:
gcc: error: unrecognized argument in option ‘-mcmodel=medany’
gcc: note: valid arguments to ‘-mcmodel=’ are: 32 kernel large medium small; did you mean ‘medium’?
…
and it carries on.
This is on a Ubuntu 18.04 system. Do you know if those instructions have been tested on Ubuntu 18.04?
I’ve tried now about 8 different “simple install” instructions and none of them ever work all the way through. All seem to fail in the final steps and I’m trying to avoid hacking away and the guesswork involved.
My objective is to be able to write C programs, compile for RV32IMA (note the absence of ‘C’ there) baremetal, and simulate; and I need to see the elf and have disassembly tools.
Any suggestions appreciated.
It seems like you are passing RISC-V compile options to a non-RISC-V gcc (x86?)
You can try riscv64-unknown-elf-gcc -print-multi-lib on the command line to see what is supported. If you are using tools from SiFive then it is likely the rv32ima string is not valid (we only build cores with ‘C’ extension enabled)
Thanks. I think I made the mistake of assuming those were instructions for building cross-compiler.
Thanks. It looks like it is what I need, but even though it seems to have installed (I get
riscv-none-embed-gcc (xPack GNU RISC-V Embedded GCC x86_64) 10.2.0
a from --version), I have not been able to get past the error below:
/opt/xpack-riscv-none-embed-gcc-10.2.0-1.2/bin/riscv-none-embed-gcc …
… /opt/xpack-riscv-none-embed-gcc-10.2.0-1.2/bin/…/lib/gcc/riscv-none-embed/10.2.0/…/…/…/…/riscv-none-embed/lib/rv32im/ilp32/libg.a(lib_a-exit.o): in function .L0 ': (.text.exit+0x2c): undefined reference to _exit’
collect2: error: ld returned 1 exit status
This is probably something for SW folks with experience in finding the right libraries and fiddling with paths and options until it works … and that might well be beyond me.
But I do appreciate the suggestion.