The EIC7700X SOC Manual claims that it supports the Hypervisor-Level ISA v0.6. The ratified version of the Hypervisor spec is v1.0. So the hardware support in the SOC is apparently a pre-standard version of the spec that may not be completely compatible with the official standard hypervisor spec. Even if it is standard conforming enough, there is no guarantee that it has been well tested, or that the software support for it exists yet. If you like bleeding edge stuff, you can try experimenting with it. But you should not assume that hypervisor support will automatically work.
thanks! Understand that it might not have been tested or even works. One other question: I see in the data sheet that cores support sv48 page tables. According to the riscv spec, i believe , implementations must support sv39 also. Do you know if this is the case ? My sw (that runs on polarfire soc w/ sv39 page table) craps out after loading satp with the sv39 table.
I’m a compiler expert, not a kernel or firmware expert. I do see a statement in Version 20240411 of the privileged spec that says “Implementations that support Sv48 must also support Sv39.” but older versions of the spec use the word “should”. So it depends on when exactly the spec changed and which version of the spec they are claiming to conform to which is probably impossible to answer. The SiFive docs for the P550 core claim it is sv39+sv48 and it doesn’t look like you can change that in Core Designer. So I would expect that the part has sv39. I do see that the EIC7700X datasheet mentions sv48 but not sv39. I don’t have access to any other useful documentation. Maybe you can look at the linux kernel sources for the board to see if it is using sv39 or sv48?
Great, thanks! My SV39 s/w is was not working but I found some issues with PTE flag bits for intermediate nodes (same code worked on polarfire SOC but I guess this version is pickier) …
Update: i have verified that the hypervisor mode works to some degree at least on this part. I can run a hypervisor (sel4) and launch V-U mode processes , so I believe the 2nd stage page table is functional. I am not convinced that hfence instruction is working (as I understand it) - I see cases where later updates to the page table don’t seem to take effect. Anyone have any experience with hfence ? (the same code does work on qemu for what that is worth)
Another issue I see with p550 and my existing code base: Anyone know of any differences between the plic on the polarfire riscv versus the plic version on this p550? My interrupt handler that works on polarfire does not seem to work properly on the p500. I can’t seem to ack the interrupt properly.
I’m considering to buy this board, the 32GB model to start a development project on it, and the way to check if everything is working as expected is running 2 or 3 VMs.
Did anyone was able to get a VM up and running? I don’t need near native performance, just something usable.
May I also ask if for RISC-V we just use common virtualization tools? Like QEMU and KVM?
thanks. I found my issue: the uart on this chip is the DW flavor of the 16550 and can generate an interrupt when the line control register is accessed (BUSY). Apparently this is often the case and usually when u-boot boots the application, it is active. So when I enabled the interrupt line in the PLIC, it immediately fired. My uart driver was not handling this extra DW interrupt (it is cleared differently than the standard uart interrupts) and so the uart was constantly interrupting the core. Getting the correct driver fixed the problem.