We would like to test TLB hardware via a bare metal C program. That requires turning on the exception handler. The ISA tests have virtual memory support, for example:
test source code: i-rocket-chip/riscv-tests/isa/rv64um/rem.S
boot sequence code: i-rocket-chip/riscv-tests/env/v/entry.S
VM setup code: i-rocket-chip/riscv-tests/env/v/vm.c
headers: i-rocket-chip/riscv-tests/env/v/riscv_test.h
Any tips on importing that into the bare metal toy benchmarks, like dhrystone?