Rocket chip riscv rtl simulation

I write a bare metal application and generate the machine code, write it to the axi memory space, and directly run the simulation, the simulation can complete.
There are some store instructions (sd, sw, etc), but the axi interface only has read actions, there’s no write actions on the axi interface for all the store instructions.
Here’s my bare metal application and the waveform, can anybody help me please?

0000000080000000 <_start>:
80000000: 30047073 csrc mstatus,8
80000004: 30405073 csrw mie,0
80000008: 00002197 auipc gp,0x2
8000000c: ff818193 add gp,gp,-8 # 80002000 <c.0>
80000010: 00003117 auipc sp,0x3
80000014: ff010113 add sp,sp,-16 # 80003000 <_sp>
80000018: 00000297 auipc t0,0x0
8000001c: 06828293 add t0,t0,104 # 80000080 <trap_vector>
80000020: 30529073 csrw mtvec,t0
80000024: 3051f073 csrc mtvec,3
80000028: 00012283 lw t0,0(sp)
8000002c: 00512423 sw t0,8(sp)
80000030: 00000513 li a0,0
80000034: 00000593 li a1,0
80000038: 7c9000ef jal 80001000
8000003c: 020010ef jal 8000105c <_postmain_fini>
80000040: 10500073 wfi
80000044: ffdff06f j 80000040 <_start+0x40>

Disassembly of section .text.trap:

0000000080000080 <trap_vector>:
80000080: f6010113 add sp,sp,-160
80000084: 00113023 sd ra,0(sp)
80000088: 00413423 sd tp,8(sp)
8000008c: 00513823 sd t0,16(sp)
80000090: 00613c23 sd t1,24(sp)
80000094: 02713023 sd t2,32(sp)
80000098: 02a13423 sd a0,40(sp)
8000009c: 02b13823 sd a1,48(sp)
800000a0: 02c13c23 sd a2,56(sp)
800000a4: 04d13023 sd a3,64(sp)
800000a8: 04e13423 sd a4,72(sp)
800000ac: 04f13823 sd a5,80(sp)
800000b0: 07013823 sd a6,112(sp)
800000b4: 07113c23 sd a7,120(sp)
800000b8: 09c13023 sd t3,128(sp)
800000bc: 09d13423 sd t4,136(sp)
800000c0: 09e13823 sd t5,144(sp)
800000c4: 09f13c23 sd t6,152(sp)
800000c8: 341022f3 csrr t0,mepc
800000cc: 06513023 sd t0,96(sp)
800000d0: 342022f3 csrr t0,mcause
800000d4: 04513c23 sd t0,88(sp)
800000d8: 34202573 csrr a0,mcause
800000dc: 00010593 mv a1,sp
800000e0: 7b1000ef jal 80001090 <core_trap_handler>
800000e4: 06013283 ld t0,96(sp)
800000e8: 34129073 csrw mepc,t0
800000ec: 05813283 ld t0,88(sp)
800000f0: 34229073 csrw mcause,t0
800000f4: 00013083 ld ra,0(sp)
800000f8: 00813203 ld tp,8(sp)
800000fc: 01013283 ld t0,16(sp)
80000100: 01813303 ld t1,24(sp)
80000104: 02013383 ld t2,32(sp)
80000108: 02813503 ld a0,40(sp)
8000010c: 03013583 ld a1,48(sp)
80000110: 03813603 ld a2,56(sp)
80000114: 04013683 ld a3,64(sp)
80000118: 04813703 ld a4,72(sp)
8000011c: 05013783 ld a5,80(sp)
80000120: 07013803 ld a6,112(sp)
80000124: 07813883 ld a7,120(sp)
80000128: 08013e03 ld t3,128(sp)
8000012c: 08813e83 ld t4,136(sp)
80000130: 09013f03 ld t5,144(sp)
80000134: 09813f83 ld t6,152(sp)
80000138: 0a010113 add sp,sp,160
8000013c: 30200073 mret

Disassembly of section .text:

0000000080001000 :
80001000: fd010113 add sp,sp,-48
80001004: 02813423 sd s0,40(sp)
80001008: 03010413 add s0,sp,48
8000100c: 00050793 mv a5,a0
80001010: fcb43823 sd a1,-48(s0)
80001014: fcf42e23 sw a5,-36(s0)
80001018: 00100793 li a5,1
8000101c: fef42623 sw a5,-20(s0)
80001020: 00200793 li a5,2
80001024: fef42423 sw a5,-24(s0)
80001028: fec42783 lw a5,-20(s0)
8000102c: 00078713 mv a4,a5
80001030: fe842783 lw a5,-24(s0)
80001034: 00f707bb addw a5,a4,a5
80001038: 0007871b sext.w a4,a5
8000103c: 00018793 mv a5,gp
80001040: 00e7a023 sw a4,0(a5)
80001044: 00018793 mv a5,gp
80001048: 0007a783 lw a5,0(a5)
8000104c: 00078513 mv a0,a5
80001050: 02813403 ld s0,40(sp)
80001054: 03010113 add sp,sp,48
80001058: 00008067 ret

000000008000105c <_postmain_fini>:
8000105c: ff010113 add sp,sp,-16
80001060: 00813423 sd s0,8(sp)
80001064: 01010413 add s0,sp,16
80001068: 010007b7 lui a5,0x1000
8000106c: 06178793 add a5,a5,97 # 1000061 <__stack_size+0xfff861>
80001070: 00779793 sll a5,a5,0x7
80001074: deadc737 lui a4,0xdeadc
80001078: eef70713 add a4,a4,-273 # ffffffffdeadbeef <_sp+0xffffffff5ead8eef>
8000107c: 00e7a023 sw a4,0(a5)
80001080: 00000013 nop
80001084: 00813403 ld s0,8(sp)
80001088: 01010113 add sp,sp,16
8000108c: 00008067 ret

0000000080001090 <core_trap_handler>:
80001090: fe010113 add sp,sp,-32
80001094: 00813c23 sd s0,24(sp)
80001098: 02010413 add s0,sp,32
8000109c: fea43423 sd a0,-24(s0)
800010a0: feb43023 sd a1,-32(s0)
800010a4: 00000793 li a5,0
800010a8: 00078513 mv a0,a5
800010ac: 01813403 ld s0,24(sp)
800010b0: 02010113 add sp,sp,32
800010b4: 00008067 ret

Disassembly of section .bss:

0000000080002000 <c.0>:
80002000: 0000 .2byte 0x0