Hello guys from SiFive Team,
I’m evaluating the E31 RTL (sifive_coreip_E31_AHB_rtl_eval_v3p0) and I’m creating my own testbench with the IP Core and a simple SRAM memory directly connected to the AHB v3 Lite bus (Master <–> Slave) peripheral port (0x2000_0000 to 0x2000_1FFF). The problem is that when I initialize the SRAM memory with the .hex file that comes with the .zip file, located at sifive_coreip_E31_AHB_rtl_eval_v3p0/tests/rv32ui-add/program.hex, the processor just stucks at 5th instruction (32’h00000197) and do not increment the PC anymore. Also, some signals from AHB bus becomes X undefined, so it has a weird behavior from master (peripheral port). I tried to use the AHBPortRAMSlave module as SRAM too but it seems the same strange behavior with the processor. Please check the following files attached. I’m using modelsim 10.6c as my digital simulator.
Do you know which can cause such problems?