I’m evaluating the E31 RTL (sifive_coreip_E31_AHB_rtl_eval_v3p0) and I’m creating my own testbench with the IP Core and a simple SRAM memory directly connected to the AHB v3 Lite bus (Master <–> Slave) peripheral port (0x2000_0000 to 0x2000_1FFF). The problem is that when I initialize the SRAM memory with the .hex file that comes with the .zip file, located at sifive_coreip_E31_AHB_rtl_eval_v3p0/tests/rv32ui-add/program.hex, the processor just stucks at 5th instruction (32’h00000197) and do not increment the PC anymore. Also, some signals from AHB bus becomes X undefined, so it has a weird behavior from master (peripheral port). I tried to use the AHBPortRAMSlave module as SRAM too but it seems the same strange behavior with the processor. Please check the following files attached. I’m using modelsim 10.6c as my digital simulator.
Hey @joryhuang are you using which SRAM behavior model for the memory connected at the peripheral port and how about the RV IP, is the same as me (E31)?
no i am not using behavior model, i use FPGA synthesizable IP to simulation.
plus, i also try E51 which interface is AXI and Vivado has the AXI interface IP, i has try to simualtion on vivado use the E51 core but also fail.
you can find my topic in this Forum.
provide a better SRAM AHB behavior model, the one’s provided by SiFive (AHBPortRAMSlave…) seems not to work properly;
Also take a look to observe that until 0x…3c the processor it’s just fetching instructions into pipe so if you want to see the processing try to add more simulation time too.
hello @aignacio have you plan to test this verilog RTL on FPGA, we want to test this RTL on our fpga, so we plan to use Vivado IP to replace the behive module, but still not success.
Hello @joryhuang I’m planning to test this in a FPGA yes, indeed I’m testing in Xilinx FPGA at this moment. I can send you a behavior model of AHB Memory, what’s your mail address?
