Error in read operation while using E31 evaluation RTL

Hi Team
Currently we have connected an SRAM to the system port and tried to write/read to the SRAM.We wrote the c program for the same, compiled and generated the hex code. We found that the write operations are working fine. But when we try to read 10 continuous locations from SRAM , it stops after reading first location. The read value is reflected in sys_port_ahb signals ,but we are not sure whether that value is loaded into the internal register. So we tried to write back the same value to the SRAM, but it is not happening. Is there any other extra steps that need to be done after the load instruction, so that the read would be complete.

Thanks in advance

Hello @simna,
How did you connect the program memory to your system? Did you attached to peripheral port one SRAM with your hex code and defined your reset vector to 32’h2000_0000? Also, how your core is instantiated at the RTL top level, which signals connect with what?

Hi @aignacio
program memory is connected to the system port and reset vector is 32’h4000_0000. core_clock and clock is given as 200 MHz, rtc_toggle is 32.76 KHz and reset is also applied. system port signals are connected to the sram. All other input signals are either tied to zero or one. screenshot of the instantiation of core is included.

Hello @simna, thanks for sharing your RTL, it seems it’s ok the connections, but could you share the program of reading/writing and indicate in what instruction it stops? Please attached the mem (verilog) file and the program itself.

Hi @aignacio
Attaching the assembly code used for reading/writing . The execution stops after the LW(load word) instruction.

The portion of the waveform is also attached.

I have included screenshot of sram code. The verilog code for AHB slave and connections with sram is too long, I couldnt take screenshot of all. I tried to upload verilog files as such, but the format is not supported here. So i f you provide your mail id ,I can share it via email

Hello @simna,

thanks for the answer, looking at your simulation screenshot seems that the memory (SRAM) is not answering to the correspondent instruction located at 0x40000148 because if we check, the processor rises up the HSEL but there isn’t data on HRDATA available to the e31 fetch, even in the latest instruction (0x40000144). Also, how exactly are you connecting the mask of your sram memory to the processor? If you fell free to send the rtl’s use the e-mail below.


Hi @aignacio,

A write operation to the location 0x40000144 and 0x40000148 is performed. The data is being read from the location 0x40000104, and it is getting reflected on the HRDATA.
Also I would like to know whether there are chances for any interrupt to trigger during read operation. Is there a way we can check the interrupt signals.

I have sent the RTL via email.

The issue resolved. The problem was the occurrence of delta delay issue while generating the clock. Thank you for the support