dear sir
i have down load the E51 RTL and run simulation in vivado.
testbench top use the ECoreIPSubsystemAllPortRAMTestHarness.sv
and only change the input clock and reset as:
module ECoreIPSubsystemAllPortRAMTestHarness(
// input clock,
// input reset,
output io_success
);
reg reset;
reg clock;
initial
begin
clock=1’b0;
reset=1’b0;
#10
reset=1’b1;
#5000
reset=1’b0;
end
always
begin
#10
clock=~clock;
end
…
i have some questions about the E51 core RTL.
- in SiFive E51 Core Complex Evaluation User Guide the system_reset_vector_0 is 64bit width but RTL is 32bit.
- what are the two signal
.debug_psd_test_mode(system_debug_psd_test_mode),
.debug_psd_test_mode_reset(system_debug_psd_test_mode_reset),
for? - when run simualtion i have write my code into ITIM ram:
data_arrays_0_ext and the data_arrays_0_0_ext; i have remove the random data generete part like below:
module data_arrays_0_0_ext(
input RW0_clk,
input [9:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
reg reg_RW0_ren;
reg [9:0] reg_RW0_addr;
reg [63:0] ram [1023:0];
initial begin
ram[0]={32’h0C85051B,32’h20000537};
ram[1]={32’h00050067,32’h00050067};
ram[2]={32’h0C85051B,32’h00050067};
end
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
if (RW0_wmask[0]) ram[RW0_addr][31:0] <= RW0_wdata[31:0];
if (RW0_wmask[1]) ram[RW0_addr][63:32] <= RW0_wdata[63:32];
end
assign RW0_rdata = ram[reg_RW0_addr];
endmodule
i force the reset vector point to ITIM(0x08000000) or DTIM(0x80000000), from the RAM interface signal has prove that only read one cycle of data the but signal of core contoller goes to XXX state.
i donot know why?
anybody has meet this problem?
thanks