I have read the Riscv ISA document, but when I use the E51 rtl to run the simulation , I can’t find which port is the PC
I’ve placed some generally useful signals when running RTL simulation. We will work on adding this information to the RTL evaluation User Guide.
io_imem_resp_(ready, valid, pc, data) → gives you the PC and Data when ready & valid are asserted together.
io_imem_req_(ready, valid, addr) → shows you when the Core wants to do a jump, but generally less useful.
xcpt* signals inside the core show you if you had some sort of Exception, to help show why it’s not progressing as you expect.