Updated E31 and E51 RISC-V Core IP Evaluations


(Drew) #1

We are happy to announce updates to the E31 and E51 evaluations!

Updates to the Arty FPGA images are as follows:

  • DTIM increased from 16kB to 64kB
  • Number of HWBP increased from 2 to 8
  • ITIM functionality added
  • User mode functionality added

Updates to the RTL evaluations are as follows:

  • Configurable ITIM
  • User mode
  • AXI4 port adapters
  • 255 interrupts
  • Updated User Manual

If you already have an evaluation license, the updates can be downloaded from your developer dashboard:
https://dev.sifive.com/dashboard/

Otherwise, you can obtain an evaluation license from the link below and scroll down to the yellow section: