Building a E51 Arty7-35T Evaluation FPGA image from scratch

Archive SiFive RISC-V Core IP Evaluation
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Is it possible to build a E51 image for the Arty7-35T evaluation board as part of the evaluation process? I would just like to build the vanilla image using the vanilla evaluation core. It wasn’t apparent to me that there is a Xilinx .xpr file that can be downloaded for the Arty 7.
Ideally, I would synthesize a functionally exact equivalent to the E51 demo eval MCS file.
If you could let me know if FPGA synthesis of the E51 demo can be part of the evaluation, I’d appreciate it.
Thanks
Rich

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Hi Richard - please refer to our email conversation to continue this thread via email.

Thanks