I have downloaded some interesting Core IP FPGA Eval Kits in https://www.sifive.com/core-designer, but I find that some prebuilt .mcs files are generated for Arty_100T. For example, the name of the .mcs file in sifive_coreip_E34_eval_dev_kit_v1p0\fpga is sifive_coreip_E34_FPGA_Evaluation_Arty_100T_v1p0_rc0.mcs.
Unfortunately, I don’t have a Arty board from Digilent or Avent. I’m using a Genesys2 boad with xc7k325t. But I still want to evaluate your cores on different Xilinx or Altera FPGA boards. I find that there are some verilog source files in “verilog/design” and “verilog/memories”, which seem could be used in Vivado or Quartus.
I have already tried out the " Freedom E300 Arty FPGA Dev Kit" from https://github.com/sifive/freedom , but I still want to evaluate more cores. So is it possible for me to use these verilog files to generate a useable bitstream file for my FPGA? Could you write some guides on how to put the FPGA Eval Kits into different FPGA boards?
As far as I know, many low-end FPGA boards from Altera are cheaper than those from Xilinx. As a result, many students/beginners would choose Altera boards rather than Xilinx boards. I think such guides will make the risc-v community more popular.
Just as background, for internal development we use VC707 ($3500) and recently VCU118 ($7000) FPGA boards. Making evaluation bitstreams available for a $250 Arty is a pretty huge cost saving and should be easily affordable by anyone doing professional work, even if they already have some other FPGA board.
Of course the equation is very different for students and the curious at home. You don’t want to be buying ten different boards.
It’s not so difficult to add support for any particular board, but there are so many different ones available, and for each one we support … we have to actually support it over time. When it comes to FPGAs from manufacturers other than Xilinx it means using different toolchains, which might cause problems in itself.
I think this is somewhere the community can help, including things such as creating a guide on how to port to different boards. All the source code for several different boards is available, so it’s possible for someone familiar with FPGA development and different boards or different toolchains to compare those and document how to do it.
I think the key point of putting SiFive Core IPs in Altera boards is replacing Xilinx primitives with Altera primitives, or replacing Xilinx IPs with Altera IPs. Besides we also have to change the constraint file for different hardware. Therefore, I think that you could tell users the Xilinx primitives and IPs you used for SiFive Core IPs, and the occupied LUTs/FFs/BRAMs/DSPs of particular SiFive Cores. In this way, users could evaluate the minimal FPGA boards they need.
Does sifive provide all sources(RTL, Constraint,non encrypted rtl, netlist) require to create xilinx vivado project from scratch.
as Developer may have custom in house developed xilinx FPGA Board or xilinx evaluation board. In such a scenario is it possible to reuse existing boards instead of sticking to boards supported/internally use by SiFive.
And it will great if sifive able to support Xilinx JTAG for processor JTAG. E.G xilinx use its JTAG for Microblaze soft processor.
This is a bit tangential, but I am also using the VC707 and I am just getting started. I am trying to step through the “SiFive Core IP FPGA Eval Kit User Guide v3p0” as far as I can with the different FPGA.
I have my PC connected to the olimex ARM-USB-TINY-H connected to the JTAG. I have the drivers for the Olimex installed. I am unsure the next steps. wsFreedomStudio only has a “Flash MCS file to ARty FPGA” button under the “SiFive_Tools” menu and this button does not detect the VC707.
Do you have advice on getting JTAG debugger working with the SiFive IP/toolchain?