Does anyone knows how to develope a SoC based on the rtl provided by the evaluation cores? I would like to develope it using the deisgn blocks of vivado, because I want to add some IP Cores.
I have done the SoC adding the rtl code of the core, but I’m not sure if it is possible to run it in an FPGA.
What steps do I have to follow to generate a SoC and Code using the GUI of Vivado?
And is the olimax cable necessary to do it? Because, what I know is with the Arty A7 the debug and FPGA program goes in the same cable.