RISC-V on arty fpga board process?

Archive SiFive RISC-V Core IP Evaluation
1

I do not know if I’m doing well.

I follow the arty fpga with riscv tutorial.
(SiFive E31/E51 Core Complex FPGA Eval Kit User Guide v2p0)
Up to chapter 4, I uploaded the MCS file to the board using Vivado.

I did everything in chapter 5, but there is nothing on the screen in the terminal.
(There is no RISC-V symbol)

Is there anything else I need to proceed?
I have seen that in the forums, I have to write a command "make upload"
Is it right?

Please help me

2

Try putting the example programs in the freedom-e-sdk onto the board.

I wasn’t able to see any output after flashing the MCS file, but programming via JTAG worked.