SiFive E51 FPGA Eval Kit v1p0

I just started testing the SiFive_E51_Coreplex_FPGA_Evaluation_v1p0_r0.mcs with release date 05/04/2017 on my Arty. It is working so far, but here are a couple of minor cleanup remarks:

The .mcs file seems to have the same bug as the older E31 .mcs file, namely that the demo program loaded with the .mcs file does not display the SiFive splash on the USB serial port as indicated in the startup guide. It only lights up an LED. Subsequently loading a corrected version of the demo_gpio program displays the SiFive splash and confirms that the memory configuration was successful and the USB serial port is also working as expected.

Minor correction to the release.txt file: although meant for the E51, the file references E31, which may tend to confuse things.

Thanks for the report Donnie! We’ll fix the note in the release.txt.

For the image software, it works for me… are you sure you have Switch 0 in the ‘off’ position (towards the edge of the board) when you press the “RESET” button? Otherwise it won’t execute the program loaded in the SPI Flash.

Hi Megan,

Yes, Switch 0 is off. I repeated the process of loading the .mcs file, and this time it worked for me as well. Lesson for me: try things at least twice before moving on. :blush:

After updating the toolchain as described in section 6.1.1. I can no longer upload any programs to the Arty, and the output from make erroneously reports “successfull” twice:

Hi, could anyone reproduce the 2.76 Coremark/MHz on E51?

I have tried, but following the CoreMark instructions in the github freedom-e-sdk Readme does not work for me. I get various “unknown type” errors from the core_list_join.c file.