I used freedom-e-sdk uploading demo programs（make software PROGRAM=demo gpio BOARD=freedom-e300-arty） by Olimex debugger ,but maybe not work. The messages:
Open On-Chip Debugger 0.10.0-dev (2017-06-28-09:19)
Licensed under GNU GPL v2
For bug reports, read http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Info : auto-selecting first available session transport “jtag”. To override use 'transport select '.
Error: no device found
Error: unable to open ftdi device with vid 15ba, pid 002a, description ‘Olimex OpenOCD JTAG ARM-USB-TINY-H’, serial ‘’ at bus location '’
Remote connection closed
"monitor" command not supported by this target.
“monitor” command not supported by this target.
You can’t do that when your target is `exec’
“monitor” command not supported by this target.
“monitor” command not supported by this target.
Successfully uploaded ‘hello’ to freedom-e300-arty.
Besides,when I used command of “make run_debug PROGRAM=demo gpio BOARD=freedom-e300-arty” running debug also report “make: *** No rule to make target ‘run_debug’. Stop.”
These two errors mean that OpenOCD was not able to talk to the Olimex adapter. It could be that it’s not plugged into USB at all, or something more complicated. This problem is not specific to RISC-V, so Google might be able to help you find the cause. Eg. this page has some troubleshooting steps at the bottom: Configuring OpenOCD with an Olimex ARM-USB-TINY-H in Ubuntu 12.04 64 bit | Andre's Technology Blog
Hi,Tim
My FPGA image contain fpga configuration file and demo program. If just need fpga configuration file?
I want to generate verilog according the command of $ make -f Makefile.e300artydevkit verilog by [https://github.com/sifive/freedom]. But, after generated verilog code add to vivado 2016.4 , when “run syn” occured some error.The prompt message is “module AsyncResetReg not found”,I don’t konw how to solve it , please tell me if you know. Thanks very much!
I add AsyncResetReg.v DebugTransportModuleJtag.v SRLatch.v into generated verilog code. The Run Synthesis is okay, but Run implention failed in vivado 2016.4 ! The prompt message is following.
I believe the bitstreams of the E310 Coreplex IP and the E300 Dev Kit are actually the same. But you can also get a bitstream for E51 Coreplex which is not part of the E300 Dev Kit, as well as Verilog RTL files for both E31 and E51. With Coreplex, you can buy your own specific configuations of the Corplex IP.
Yes, I have successfully tried debugging on the Arty using the Olimex “ARM-USB-TINY-H” debugger.
I have used the Olimex debugger using bioth freedom-e-sdk and FreedomStudio, on Corplex IP only. I have not yet been able to get my own Chisel generated bitstream to work.
You operating system is linux ? I always debug failed. The Olimex debugger need installing driver in windows ? The wire between debugger and computer is okay.
I have successfully used the Olimex debugger on a Linux virtual machine running on a Windows 7 machine, on the Windows 7 machine directly using the FreedomStudio for Windows, and also on Windows 7 running Cygwin (see this thread).
On Linux, is your Olimex appearing in the devices list as described in chapter 4 of the getting started guide?
Can you tell me the difference between Coreplex IP and Freedom E300 Dev Kit ? If you try debug with "ARM-USB-TINY-H" ? Thanks agin !
Donnie is right. Just to add some more detail, you can think of the Freedom E300 Dev Kit (downloaded from here: https://dev.sifive.com/freedom-soc/evaluate/fpga/) as an FPGA version of the FE310 chip. As such, it is using a slightly older version of the Debug protocol, and has a different JTAG IDCODE, and has peripherals and pinout to match the FE310. All this is handled automatically when you say BOARD=freedom-e300-arty. And if you build your own MCS file from the Freedom repository (github.com/sifive/freedom), you should use the same BOARD argument.
The E31 Coreplex IP FPGA Dev Kit (downloaded from here: https://dev.sifive.com/coreplex-risc-v-ip/evaluate/fpga/) uses a newer version of the Debug protocol, has a different JTAG IDCODE, and has different peripherals. Which is why you should use BOARD=coreplexip-e31-arty (or e51) when using those MCS files.
Your explanation deepen my understanding of the difference between coreplexip e31 and freedom e300 dev kit. So，I have another question. I have generated Verilog code in the directory of freedom (www.github.com/sifive/freedom ) is coreplex ip or freedom e300 dev kit ？How to ge FPGA bitstream file not contain demo program？
Your advice every time always help me a lot ! my Olimex appearing in the devices list as described in chapter 4 of the getting started guide, but debug always failed ! Thanks again !
