Freedom Studio on Linux


(Nauman) #1

Hi, I downloaded freedom studio linux version from SiFive. I am not sure what is the problem here. When I try to import demo program nothing is imported although the project folder is created in workspace. I then load project files from the file menu. But the project shows that something is wrong with .c file. it’s empty and I am not even getting the option to edit it. I tried to search internet but got nothing. I am using ubuntu 16.04. Any idea?


(Drew) #2

How are you importing the projects? Please be sure to follow the instructions detailed in Chapter 4 of the manual:


(Nauman) #3

Hi, Thank you for the reply. I got it right now but still could not run coreplex_welcome example. When I run it it shows (exit value:127) coreplexip_welcome.elf[C/C++ Application]. Any idea? One more thing is it necessary to connect debug cable if you are not going to run it in debug mode? I have USB cable only.


(Drew) #4

If you are using the Arty board, then yes the Olimex JTAG adapter is required for both loading applications and debugging them.

If you are using a HiFive1, then only a usb cable is necessary.


(Nauman) #5

Hi, Thank you for the reply. I was just wondering is there any way to upload the sdk application using usb cable? One more question current Freedom repo from github does not include demo program in mcs. Can you please guide how can I include my sdk program in mcs file in freedom repo?


(Megan A. Wachs) #6

If you have the ELF file generated from Freedom Studio, you can include it in your MCS file by following the instructions in this thread to point to your elf file:


(Nauman) #7

Hi, Thanks for the help. I followed the procedure. I created .bin file for coreplexip_welcome example. I then created mcs file from freedom repo and uploaded it using vivado. I could see three yellow led on but nothing on the serial. Below is what i got when I created mcs file. Not sure what is the problem. Any idea?
Creating config memory files…
Creating bitstream load up from address 0x00000000
Loading bitfile obj/system.bit
Creating bitstream load up from address 0x00400000
Loading datafile /home/anbuntu/freedom/fpga/e300artydevkit/coreplexip_welcome.bin
Writing file obj/system.mcs
Writing log file obj/system.prm

Configuration Memory information

File Format MCS
Interface SPIX4
Size 16M
Start Address 0x00000000
End Address 0x00FFFFFF

Addr1 Addr2 Date File(s)
0x00000000 0x0021728B Aug 16 09:48:00 2017 obj/system.bit
0x00400000 0x004010C7 Aug 16 09:31:45 2017 /home/anbuntu/freedom/fpga/e300artydevkit/coreplexip_welcome.bin
0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
INFO: [Common 17-206] Exiting Vivado at Wed Aug 16 09:48:34 2017…
make[1]: Leaving directory '/home/anbuntu/freedom/fpga/e300artydevkit’
cp /home/anbuntu/freedom/fpga/e300artydevkit/obj/system.mcs /home/anbuntu/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.mcs


(Megan A. Wachs) #8

How are the switches set on your Arty board? You will need to make sure they are set properly to get the correct reset vector for the program to execute automatically.


(Nauman) #9

Hi, Thank you for the reply. Manual talks about Switch 0 only and I am keeping it at Off position (towards the edge of the board). JP1 is inserted in too. Just let me explain what I have done until now.I still have not got Olimex cable. So I import the coreplexip_welcome example in Freedom studio. I can build it in debug mode but get errors in Release mode. I then use the generated elf file from debug mode to built bin file using the following command riscv32-unknown-elf-objcopy -O binary coreplexip_welcome.elf coreplexip_welcome.bin. Since I am using prebuilt tool chain from Sifive and there is no riscv32 in it so I am using riscv32 from riscv-tool that I built earlier. I then copy this bin file to fpga folder in freedom repo and followed the procedure you mention earlier.When I upload mcs file in ARTY ld4,ld5 and ld6 are on but nothing on the serial. One more thing when I check terminal executing MakeFile.e300artydevkit in freedom it shows warning [DRC RPBF-3] IO buffering is incomplete for Device port clk_io[14],led_0,led_1 and led_2.


(Nauman) #10

Hi, Just an update. I just got Olimex cable and I can upload example program using the mcs file provided by Sifive. But when I used the mcs I generated using Freedom repo I get following error:
Open On-Chip Debugger 0.10.0-dev-g0d86772-dirty (2017-06-13-14:13)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Info : auto-selecting first available session transport “jtag”. To override use 'transport select '.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x10e31913 (mfg: 0x489 (), part: 0x0e31, ver: 0x1)
Warn : JTAG tap: riscv.cpu UNEXPECTED: 0x10e31913 (mfg: 0x489 (), part: 0x0e31, ver: 0x1)
Error: JTAG tap: riscv.cpu expected 1 of 1: 0x20000001 (mfg: 0x000 (), part: 0x0000, ver: 0x2)
Error: Trying to use configured scan chain anyway…
Warn : Bypassing JTAG setup events due to errors
halted at 0x404 due to software breakpoint
Info : Examined RISCV core; XLEN=32, misa=0x40001105
Error: Core got an exception (0xffffffff) while writing to 0x20004050
Error: FESPI_WRITE_REG error
Error: auto_probe failed
Thanks a lot for your time.


(cailinlin) #11

Did you solve this problem now, I have the same problem, can you help me to answer it?


(Cesare Garlati) #12

Same here:

Info : JTAG tap: riscv.cpu tap/device found: 0x10e31913 (mfg: 0x489 (SiFive, Inc.), part: 0x0e31, ver: 0x1)
Warn : JTAG tap: riscv.cpu UNEXPECTED: 0x10e31913 (mfg: 0x489 (SiFive, Inc.), part: 0x0e31, ver: 0x1)
Error: JTAG tap: riscv.cpu expected 1 of 1: 0x20000001 (mfg: 0x000 (), part: 0x0000, ver: 0x2)

What is the correct arty-35t mcs file compatible with Freedom Studio setup?

Thanks!

Cesare


(Megan A. Wachs) #13

It depends what you put on your Arty FPGA. How did you generate/where did you get the MCS file that you have put on your Arty board?

Megan


(Cesare Garlati) #14

Hi Megan,

sifive_coreip_E31_FPGA_Evaluation_v2p0_0.mcs is the only one that I am able to use with Freedom Studio.

freedom-e310-arty-1-0-2.mcs and E300ArtyDevKitFPGAChip.mcs work on the arty but not in conjunction with Freedom Studio.

Thanks!

Cesare


(Megan A. Wachs) #15

Yes, you are correct that the E300 Arty Dev Kit does not have any example projects in Freedom Studio. You can start with a HiFive1 example project, then correct the openocd.cfg script and some things within the software (you can see the differences between the two in the Freedom E SDK).


(Cesare Garlati) #16

It works! Thanks Cesare

Note for future readers of this post: here is a quick recap of mcs, jtag id and board config

E300ArtyDevKitFPGAChip.mcs
https://github.com/sifive/freedom
JTAG=0x20000913
BOARD=freedom-e300-arty
(See Freedom E300 MCS file not working)

freedom-e310-arty-1-0-2.mcs
https://github.com/sifive/freedom
JTAG=0x10e31913
BOARD=freedom-e300-arty

sifive_coreip_E31_FPGA_Evaluation_v2p0_0.mcs
https://dev.sifive.com/dashboard/deliverables/sifive_e31_fpga_eval_kit_bitstream/releases/v2p0/download
JTAG=0x20000001
BOARD=coreplexip-e31-arty


(Stevan Ignjatovic) #17

Hello,

I built mcs E300ArtyDevKitFPGAChip.mcs file from https://github.com/sifive/freedom. I also made changes to openocd .cfg file according to instructions from Freedom E300 MCS file not working. However, although everything works fine with sifive_coreip_E31_FPGA_Evaluation_v2p0_0.mcs i still cannot upload and debug an application with E300ArtyDevKitFPGAChip.mcs.

I have to note that I am using JTAG debugger C232HM instead of recommended Olimex JTAG debugger, and it works fine with sifive_coreip_E31_FPGA_Evaluation_v2p0_0.mcs.

This is the output from the debug console:

Open On-Chip Debugger 0.10.0+dev-gdd0dd7f64e03-dirty (2018-01-09-17:24)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : auto-selecting first available session transport “jtag”. To override use 'transport select '.
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Info : dtmcontrol_idle=5, dmi_busy_delay=1, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=2, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=3, ac_busy_delay=0
Info : Disabling abstract command reads from CSRs.
Info : Disabling abstract command writes to CSRs.
Info : [0] Found 2 triggers
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, 2 triggers
Info : Listening on port 3333 for gdb connections
Started by GNU MCU Eclipse
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting ‘gdb’ connection on tcp/3333
Info : Found flash device ‘micron n25q128’ (ID 0x0018ba20)
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive, Inc.), part: 0x0000, ver: 0x2)
Info : dtmcontrol_idle=5, dmi_busy_delay=4, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=5, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=6, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=7, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=8, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=9, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=10, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=12, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=14, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=16, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=18, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=20, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=23, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=26, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=29, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=32, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=36, ac_busy_delay=0
Info : dropped ‘gdb’ connection

Does anybody have idea what is the problem?

Thanks,
Stavan


(Megan A. Wachs) #18

Hi Stavan,

Not sure how you are launching OpenOCD / GDB or which versions of the tools you are using (are you using Freedom Studio?). You may want to add the -d flag to the OpenOCD command line so that you can get debug output. It looks like GDB is the one that is having the problem, so you may want to look at the GDB console to see what messages you get.

Mostly it looks like things are working, but there is a problem after reset is asserted by OpenOCD.


#20

I have the same issue. Any solutions yet?


#21

Debug: 7177 483 riscv-013.c:1704 write_memory(): writing until final address 0x0000000040400014
Debug: 7178 483 riscv-013.c:1707 write_memory(): transferring burst starting at address 0x0000000040400000
Debug: 7179 483 riscv-013.c:1742 write_memory(): M[0x40400000] writes 0x3fc01197
Debug: 7180 483 riscv-013.c:924 register_write_direct(): [0] reg[0x8] <- 0x40400000
Debug: 7181 483 riscv-013.c:265 scan(): 41b w 40400000 @04 -> + 00000000 @00
Debug: 7182 483 riscv-013.c:265 scan(): 41b - 00000000 @04 -> + 80000944 @04
Debug: 7183 483 riscv-013.c:564 execute_abstract_command(): command=0x231008
Debug: 7184 483 riscv-013.c:265 scan(): 41b w 00231008 @17 -> + 00000000 @00
Debug: 7185 484 riscv-013.c:265 scan(): 41b - 00000000 @17 -> + 00221009 @17
Debug: 7186 484 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7187 484 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000001 @16
Debug: 7188 484 riscv-013.c:276 scan(): -> progbufsize=16 datacount=1
Debug: 7189 484 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7190 484 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000001 @16
Debug: 7191 484 riscv-013.c:276 scan(): -> progbufsize=16 datacount=1
Debug: 7192 484 riscv-013.c:265 scan(): 41b w 3fc01197 @04 -> + 00000000 @00
Debug: 7193 484 riscv-013.c:265 scan(): 41b - 00000000 @04 -> + 40400000 @04
Debug: 7194 484 riscv-013.c:564 execute_abstract_command(): command=0x271009
Debug: 7195 484 riscv-013.c:265 scan(): 41b w 00271009 @17 -> + 00000000 @00
Debug: 7196 484 riscv-013.c:265 scan(): 41b - 00000000 @17 -> + 00231008 @17
Debug: 7197 484 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7198 484 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000301 @16
Debug: 7199 484 riscv-013.c:276 scan(): -> progbufsize=16 cmderr=3 datacount=1
Debug: 7200 484 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7201 484 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000301 @16
Debug: 7202 484 riscv-013.c:276 scan(): -> progbufsize=16 cmderr=3 datacount=1
Debug: 7203 484 riscv-013.c:575 execute_abstract_command(): command 0x271009 failed; abstractcs=0x10000301
Debug: 7204 485 riscv-013.c:265 scan(): 41b w 00000300 @16 -> + 00000000 @00
Debug: 7205 485 riscv-013.c:276 scan(): cmderr=3 ->
Debug: 7206 485 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000301 @16
Debug: 7207 485 riscv-013.c:276 scan(): -> progbufsize=16 cmderr=3 datacount=1
Debug: 7208 485 riscv-013.c:265 scan(): 41b w 00000000 @18 -> + 00000000 @00
Debug: 7209 485 riscv-013.c:265 scan(): 41b - 00000000 @18 -> + 00000000 @18
Debug: 7210 485 riscv-013.c:924 register_write_direct(): [0] reg[0x9] <- 0x80000944
Debug: 7211 485 riscv-013.c:265 scan(): 41b w 80000944 @04 -> + 00000000 @00
Debug: 7212 485 riscv-013.c:265 scan(): 41b - 00000000 @04 -> + 3fc01197 @04
Debug: 7213 485 riscv-013.c:564 execute_abstract_command(): command=0x231009
Debug: 7214 485 riscv-013.c:265 scan(): 41b w 00231009 @17 -> + 00000000 @00
Debug: 7215 485 riscv-013.c:265 scan(): 41b - 00000000 @17 -> + 00271009 @17
Debug: 7216 485 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7217 485 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000001 @16
Debug: 7218 485 riscv-013.c:276 scan(): -> progbufsize=16 datacount=1
Debug: 7219 485 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7220 485 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000001 @16
Debug: 7221 485 riscv-013.c:276 scan(): -> progbufsize=16 datacount=1
Debug: 7222 485 riscv-013.c:924 register_write_direct(): [0] reg[0x8] <- 0x400
Debug: 7223 486 riscv-013.c:265 scan(): 41b w 00000400 @04 -> + 00000000 @00
Debug: 7224 486 riscv-013.c:265 scan(): 41b - 00000000 @04 -> + 80000944 @04
Debug: 7225 486 riscv-013.c:564 execute_abstract_command(): command=0x231008
Debug: 7226 486 riscv-013.c:265 scan(): 41b w 00231008 @17 -> + 00000000 @00
Debug: 7227 486 riscv-013.c:265 scan(): 41b - 00000000 @17 -> + 00231009 @17
Debug: 7228 486 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7229 486 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000001 @16
Debug: 7230 486 riscv-013.c:276 scan(): -> progbufsize=16 datacount=1
Debug: 7231 486 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7232 486 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000001 @16
Debug: 7233 486 riscv-013.c:276 scan(): -> progbufsize=16 datacount=1
Debug: 7234 486 program.c:33 riscv_program_write(): 0x7ffe5c147780: debug_buffer[00] = DASM(0x0000000f)
Debug: 7235 486 riscv-013.c:265 scan(): 41b w 0000000f @20 -> + 00000000 @00
Debug: 7236 486 riscv-013.c:265 scan(): 41b - 00000000 @20 -> + 00942023 @20
Debug: 7237 486 program.c:33 riscv_program_write(): 0x7ffe5c147780: debug_buffer[01] = DASM(0x00100073)
Debug: 7238 486 riscv-013.c:265 scan(): 41b w 00100073 @21 -> + 00000000 @00
Debug: 7239 486 riscv-013.c:265 scan(): 41b - 00000000 @21 -> + 00440413 @21
Debug: 7240 486 riscv-013.c:564 execute_abstract_command(): command=0x241000
Debug: 7241 486 riscv-013.c:265 scan(): 41b w 00241000 @17 -> + 00000000 @00
Debug: 7242 487 riscv-013.c:265 scan(): 41b - 00000000 @17 -> + 00231008 @17
Debug: 7243 487 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7244 487 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000001 @16
Debug: 7245 487 riscv-013.c:276 scan(): -> progbufsize=16 datacount=1
Debug: 7246 487 riscv-013.c:265 scan(): 41b r 00000000 @16 -> + 00000000 @00
Debug: 7247 487 riscv-013.c:265 scan(): 41b - 00000000 @16 -> + 10000001 @16
Debug: 7248 487 riscv-013.c:276 scan(): -> progbufsize=16 datacount=1
Debug: 7249 487 gdb_server.c:2846 gdb_input_inner(): received packet: 'X40400018,236:'
Debug: 7250 487 gdb_server.c:1371 gdb_error(): Reporting -4 to GDB as generic error
Debug: 7251 487 gdb_server.c:1554 gdb_write_memory_binary_packet(): addr: 0x40400018, len: 0x00000236
Debug: 7252 487 target.c:2051 target_write_buffer(): writing buffer of 566 byte at 0x40400018
Debug: 7253 487 riscv-013.c:1659 write_memory(): writing 141 words of 4 bytes to 0x40400018
Debug: 7254 487 riscv-013.c:564 execute_abstract_command(): command=0x221008

I have the same issue. I built mcs file from github! It says MI command failed?