Freedom E300 port to zedboard


#1

Hi everyone,

I would like to port Freedom E300 platform to zedboard, could anyone give me a pointer on how to do that? Or has anyone done this before?

Thanks,
Ken


(dh73) #2

Hi,

The way in which the Chisel Freedom project for Xilinx platforms is pretty straight forward. I will suggest you to run the project for Arty board in GUI mode and become familiar with the structure of it. Most probably you’ll need to change only device family (Zynq) and pin assignments and that’s it.

You can try it and ask for any help if something goes wrong.


#3

The repo is updated recently (I think 1 day ago?), and the flow based on README is no longer working, do you know how we get the GUI mode flow based on this repo?


(Megan A. Wachs) #4

Hi @dong, what do you mean that the flow based on the README is not working? Can you share what error you get? You can generate the verilog as directed by the README, then use your usual Zedboard flow to instantiate the Verilog. We’ve moved to an all-Chisel top level file, but you can still modify/replace either the generated Verilog or Chisel top-level that matches your ZedBoard’s top level.


#5

Hi Megan,

Thanks for your reply. I got the error when I try to generate the mcs file as per README:


File “/projects/freedom0821/freedom/rocket-chip/scripts/vlsi_rom_gen”, line 114
for key, val in iterate_by_n(line.split(), 2)}
^
SyntaxError: invalid syntax
make1: *** /projects/freedom0821/freedom/builds/e300artydevkit/rom.v Error 1
make1: Leaving directory `/projects/digital/work/ken/freedom0821/freedom/bootrom/xip’
make: *** /projects/freedom0821/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.rom.v Error 2

Also, for porting e300 to zedboard, I was a bit confused about what I need to do, so for the current flow, I used all the Chisel top level to generate the top level HDL wrapper, and I just modified the pin assignment in arty-master.xdc to match the pins in zedboard. Is that it? Or did I miss anything?

Thanks.
Dong


(Megan A. Wachs) #6

Please check your Python version (see https://github.com/sifive/freedom/issues/32)

Your method of porting to the Zedboard sounds fine to me!


#9

Hi @mwachs5,

I am running into two problems, the first one is console access for E300.

  1. In Arty board, this is done by USB-UART cable (in FPGA), but in zedboard, we don’t have access to USB-UART interface via Programmable Logic (PL), but only Processing System (PS). How do we deal with that in this case?

  2. Similarly, E300 is booted via Quad SPI (which is built-in chip on FPGA board), but in zedboard, we also don’t have access to SPI via PL. That means we can’t boot E300 in PL. How do we deal with it?

Thanks,
Dong


(Megan A. Wachs) #10
  1. I am not too familiar with the Zedboard, but if you are already using the Olimex debugging dongle, you can connect up the other interface for UART connectivity. You would need to modify your FPGA constraints file to put the UART RX/TX lines out to pins similar to the JTAG pins, and hook them to the appropriate pins on the Olimex header.

  2. If you want to boot from SPI and can’t access the one on the ZedBoard, you may need to connect an external SPI Flash device and again adjust the qspi pin interface to hook to those.

There may be a better answer from someone more familiar with the ZedBoard.


(Bruce Hoult) #11

I’m not … but I’m interested in the answer because it’s probably going to apply to the Arty Z7 as well.


#12

Hi @mwachs5,

I have modified the constraint file of the zedboard so that all the pins are lined up, but when I connect the JTAG to PMOD header (I mapped JTAG to PMOD D header, which is same as Arty) and upload an gpio_demo program via freedom-e-sdk, I got the following errors:

adapter speed: 10000 kHz
Info : auto-selecting first available session transport “jtag”. To override use 'transport select '.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway…
Error: riscv.cpu: IR capture error; saw 0x1f not 0x01
Warn : Bypassing JTAG setup events due to errors
Error: Unsupported DTM version: 15
Error: Target not examined yet

Remote communication error. Target disconnected.: Connection reset by peer.
“monitor” command not supported by this target.
“monitor” command not supported by this target.
You can’t do that when your target is `exec’
“monitor” command not supported by this target.
“monitor” command not supported by this target.
Successfully uploaded ‘hello’ to freedom-e300-arty.

I have checked my wiring between the debugger and the PMOD on the zedboard twice, and it looked fine. What would be the potential issue?

Thanks,
Dong


(Megan A. Wachs) #13

Hmmm, I would check the reset connections. Also is it possible for you to see if the TCK, TDI, TMS lines are wiggling (perhaps by connecting to some LEDs on the ZedBoard)?

You could post a picture of your debugger setup.


#14

Hi @mwachs5,

I think I find out the reason (but not sure if that is exactly it). Before that, may I ask if the master clock (the clock of Arty) needs to be running for the JTAG interface to work even though TCK is from development system (PC) anyway?

I am asking because when I synthesise it, I got the warning that no clock is inferred in the design, because in order to use clock in FPGA fabric, one needs to initialise the ARM side of zynq to get the clock running on PL side.

Thanks,
Dong


(Megan A. Wachs) #15

The core clock will need to be running in order to do anything interesting with the JTAG, but you should be able to at least read the DTM registers without any other clock but TCK running.

You could make a PR of your Zedboard port to github.com/sifive/fpga-shells repo and it would be easier to see what could be going wrong.


#16

Thanks @mwachs5, I have routed it TDO to one of the LEDs on the zedboard, and I have changed the frequency of JTAG (in the open_ocd configuration file) to 1KHz. When I am trying to upload a program to RISC-V core to debugger, I can see the led is on for ~0.5s and off. Does the mean we have a good connectivity on JTAG?

But I am still getting the error similar to the thread here:

Info : dtmcontrol_idle=5, dmi_busy_delay=1, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=2, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=3, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=4, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=5, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=6, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=7, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=8, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=9, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=10, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=12, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=14, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=16, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=18, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=20, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=23, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=26, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=29, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=32, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=36, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=40, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=45, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=50, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=56, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=62, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=69, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=76, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=84, ac_busy_delay=0
Info : dtmcontrol_idle=5, dmi_busy_delay=93, ac_busy_delay=0

I have followed your suggestions in this thread and modified the configuration file, and the error is gone, but then I got:

Remote connection closed
"monitor" command not supported by this target.
“monitor” command not supported by this target.
You can’t do that when your target is `exec’
“monitor” command not supported by this target.
“monitor” command not supported by this target.

and nothing gets uploaded. When I run “make run_openocd PROGRAM=hello BOARD=freedom-e300-arty”, it just got seg falut. How do I resolve this error? I am wondering if this is something to do with the flash. Thins I have done:

Plug in an EXTERNAL flash, and route the qspi pins in the constraint correspondingly. Do we need to change any configuration other than constraint?

Any suggestions would be much appreciated! Thanks!

Dong


(Megan A. Wachs) #17

Why not try running OpenOCD manually and adding the ‘-d’ flag:

$RISCV_OPENOCD_PATH/bin/openocd -f openocd.cfg -d

This will just connect without trying to load anything the flash. Can you give it a try and post your log?


#18

Hi @mwachs5,

Thanks for the guide. The log is as follows when I run the command suggested above:

Debug: 14 2 options.c:96 add_default_dirs(): bindir=/home/palmer/riscv-binary-tools/obj/x86_64-linux-centos6/install/riscv-openocd-20170612-x86_64-linux-centos6/bin
Debug: 15 2 options.c:97 add_default_dirs(): pkgdatadir=/home/palmer/riscv-binary-tools/obj/x86_64-linux-centos6/install/riscv-openocd-20170612-x86_64-linux-centos6/share/openocd
Debug: 16 2 options.c:98 add_default_dirs(): run_prefix=
Debug: 17 2 configuration.c:42 add_script_search_dir(): adding /home/ken/.openocd
Debug: 18 2 configuration.c:42 add_script_search_dir(): adding /home/palmer/riscv-binary-tools/obj/x86_64-linux-centos6/install/riscv-openocd-20170612-x86_64-linux-centos6/share/openocd/site
Debug: 19 2 configuration.c:42 add_script_search_dir(): adding /home/palmer/riscv-binary-tools/obj/x86_64-linux-centos6/install/riscv-openocd-20170612-x86_64-linux-centos6/share/openocd/scripts
Debug: 20 2 configuration.c:82 find_file(): found ./bsp/env/freedom-e300-arty/openocd.cfg
Debug: 21 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 1
Debug: 22 2 command.c:143 script_debug(): command - adapter_khz ocd_adapter_khz 1
Debug: 24 2 core.c:1745 jtag_config_khz(): handle jtag khz
Debug: 25 2 core.c:1712 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 26 2 core.c:1712 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 27 2 command.c:544 command_print(): adapter speed: 1 kHz
Debug: 28 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_interface ftdi
Debug: 29 2 command.c:143 script_debug(): command - interface ocd_interface ftdi
Debug: 31 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_device_desc’…
Debug: 32 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_serial’…
Debug: 33 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_channel’…
Debug: 34 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_layout_init’…
Debug: 35 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_layout_signal’…
Debug: 36 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_set_signal’…
Debug: 37 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_get_signal’…
Debug: 38 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_vid_pid’…
Debug: 39 2 command.c:364 register_command_handler(): registering ‘ocd_ftdi_tdo_sample_edge’…
Debug: 40 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_device_desc Olimex OpenOCD JTAG ARM-USB-TINY-H
Debug: 41 2 command.c:143 script_debug(): command - ftdi_device_desc ocd_ftdi_device_desc Olimex OpenOCD JTAG ARM-USB-TINY-H
Debug: 43 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_vid_pid 0x15ba 0x002a
Debug: 44 2 command.c:143 script_debug(): command - ftdi_vid_pid ocd_ftdi_vid_pid 0x15ba 0x002a
Debug: 46 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_init 0x0808 0x0a1b
Debug: 47 2 command.c:143 script_debug(): command - ftdi_layout_init ocd_ftdi_layout_init 0x0808 0x0a1b
Debug: 49 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nSRST -oe 0x0200
Debug: 50 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nSRST -oe 0x0200
Debug: 52 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
Debug: 53 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
Debug: 55 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal LED -data 0x0800
Debug: 56 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal LED -data 0x0800
Debug: 58 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 59 3 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Info : 60 3 transport.c:286 jim_transport_select(): auto-selecting first available session transport “jtag”. To override use 'transport select '.
Debug: 61 3 command.c:364 register_command_handler(): registering ‘ocd_jtag_flush_queue_sleep’…
Debug: 62 3 command.c:364 register_command_handler(): registering ‘ocd_jtag_rclk’…
Debug: 63 3 command.c:364 register_command_handler(): registering ‘ocd_jtag_ntrst_delay’…
Debug: 64 3 command.c:364 register_command_handler(): registering ‘ocd_jtag_ntrst_assert_width’…
Debug: 65 3 command.c:364 register_command_handler(): registering ‘ocd_scan_chain’…
Debug: 66 3 command.c:364 register_command_handler(): registering ‘ocd_jtag_reset’…
Debug: 67 3 command.c:364 register_command_handler(): registering ‘ocd_runtest’…
Debug: 68 3 command.c:364 register_command_handler(): registering ‘ocd_irscan’…
Debug: 69 3 command.c:364 register_command_handler(): registering ‘ocd_verify_ircapture’…
Debug: 70 3 command.c:364 register_command_handler(): registering ‘ocd_verify_jtag’…
Debug: 71 3 command.c:364 register_command_handler(): registering ‘ocd_tms_sequence’…
Debug: 72 3 command.c:364 register_command_handler(): registering ‘ocd_wait_srst_deassert’…
Debug: 73 3 command.c:364 register_command_handler(): registering ‘ocd_jtag’…
Debug: 74 3 command.c:364 register_command_handler(): registering ‘ocd_jtag’…
Debug: 86 3 command.c:364 register_command_handler(): registering ‘ocd_svf’…
Debug: 87 3 command.c:364 register_command_handler(): registering ‘ocd_xsvf’…
Debug: 88 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 89 3 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 90 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag newtap riscv cpu -irlen 5 -expected-id 0x10e31913
Debug: 91 3 command.c:143 script_debug(): command - ocd_jtag ocd_jtag newtap riscv cpu -irlen 5 -expected-id 0x10e31913
Debug: 92 3 tcl.c:549 jim_newtap_cmd(): Creating New Tap, Chip: riscv, Tap: cpu, Dotted: riscv.cpu, 4 params
Debug: 93 3 tcl.c:573 jim_newtap_cmd(): Processing option: -irlen
Debug: 94 3 tcl.c:573 jim_newtap_cmd(): Processing option: -expected-id
Debug: 95 3 core.c:1418 jtag_tap_init(): Created Tap: riscv.cpu @ abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 96 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target create riscv.cpu riscv -chain-position riscv.cpu
Debug: 97 3 command.c:143 script_debug(): command - ocd_target ocd_target create riscv.cpu riscv -chain-position riscv.cpu
Debug: 98 3 target.c:1894 target_free_all_working_areas_restore(): freeing all working areas
Debug: 99 3 command.c:364 register_command_handler(): registering ‘ocd_riscv.cpu’…
Debug: 100 3 command.c:364 register_command_handler(): registering ‘ocd_riscv.cpu’…
Debug: 101 3 command.c:364 register_command_handler(): registering ‘ocd_riscv.cpu’…
Debug: 118 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
Debug: 119 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
Debug: 120 3 target.c:1894 target_free_all_working_areas_restore(): freeing all working areas
Debug: 121 3 target.c:1894 target_free_all_working_areas_restore(): freeing all working areas
Debug: 122 3 target.c:1894 target_free_all_working_areas_restore(): freeing all working areas
Debug: 123 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash bank my_first_flash fespi 0x20000000 0 0 0 riscv.cpu
Debug: 124 3 command.c:143 script_debug(): command - ocd_flash ocd_flash bank my_first_flash fespi 0x20000000 0 0 0 riscv.cpu
Debug: 126 3 fespi.c:177 fespi_flash_bank_command(): fespi_flash_bank_command
Debug: 127 3 tcl.c:1032 handle_flash_bank_command(): ‘fespi’ driver usage field missing
Debug: 128 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_init
Debug: 129 3 command.c:143 script_debug(): command - init ocd_init
Debug: 131 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target init
Debug: 132 3 command.c:143 script_debug(): command - ocd_target ocd_target init
Debug: 134 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 135 3 command.c:143 script_debug(): command - ocd_target ocd_target names
Debug: 136 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu cget -event gdb-flash-erase-start
Debug: 137 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu cget -event gdb-flash-erase-start
Debug: 138 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 139 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu configure -event gdb-flash-erase-start reset init
Debug: 140 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu cget -event gdb-flash-write-end
Debug: 141 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu cget -event gdb-flash-write-end
Debug: 142 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 143 3 command.c:143 script_debug(): command - ocd_riscv.cpu ocd_riscv.cpu configure -event gdb-flash-write-end reset halt
Debug: 144 3 target.c:1319 handle_target_init_command(): Initializing targets…
Debug: 145 3 riscv.c:246 riscv_init_target(): riscv_init_target()
Debug: 146 3 command.c:364 register_command_handler(): registering ‘ocd_target_request’…
Debug: 147 3 command.c:364 register_command_handler(): registering ‘ocd_trace’…
Debug: 148 3 command.c:364 register_command_handler(): registering ‘ocd_trace’…
Debug: 149 3 command.c:364 register_command_handler(): registering ‘ocd_fast_load_image’…
Debug: 150 4 command.c:364 register_command_handler(): registering ‘ocd_fast_load’…
Debug: 151 4 command.c:364 register_command_handler(): registering ‘ocd_profile’…
Debug: 152 4 command.c:364 register_command_handler(): registering ‘ocd_virt2phys’…
Debug: 153 4 command.c:364 register_command_handler(): registering ‘ocd_reg’…
Debug: 154 4 command.c:364 register_command_handler(): registering ‘ocd_poll’…
Debug: 155 4 command.c:364 register_command_handler(): registering ‘ocd_wait_halt’…
Debug: 156 4 command.c:364 register_command_handler(): registering ‘ocd_halt’…
Debug: 157 4 command.c:364 register_command_handler(): registering ‘ocd_resume’…
Debug: 158 4 command.c:364 register_command_handler(): registering ‘ocd_reset’…
Debug: 159 4 command.c:364 register_command_handler(): registering ‘ocd_soft_reset_halt’…
Debug: 160 4 command.c:364 register_command_handler(): registering ‘ocd_step’…
Debug: 161 4 command.c:364 register_command_handler(): registering ‘ocd_mdw’…
Debug: 162 4 command.c:364 register_command_handler(): registering ‘ocd_mdh’…
Debug: 163 4 command.c:364 register_command_handler(): registering ‘ocd_mdb’…
Debug: 164 4 command.c:364 register_command_handler(): registering ‘ocd_mww’…
Debug: 165 4 command.c:364 register_command_handler(): registering ‘ocd_mwh’…
Debug: 166 4 command.c:364 register_command_handler(): registering ‘ocd_mwb’…
Debug: 167 4 command.c:364 register_command_handler(): registering ‘ocd_bp’…
Debug: 168 4 command.c:364 register_command_handler(): registering ‘ocd_rbp’…
Debug: 169 4 command.c:364 register_command_handler(): registering ‘ocd_wp’…
Debug: 170 4 command.c:364 register_command_handler(): registering ‘ocd_rwp’…
Debug: 171 4 command.c:364 register_command_handler(): registering ‘ocd_load_image’…
Debug: 172 4 command.c:364 register_command_handler(): registering ‘ocd_dump_image’…
Debug: 173 4 command.c:364 register_command_handler(): registering ‘ocd_verify_image’…
Debug: 174 4 command.c:364 register_command_handler(): registering ‘ocd_test_image’…
Debug: 175 4 command.c:364 register_command_handler(): registering ‘ocd_reset_nag’…
Debug: 176 4 command.c:364 register_command_handler(): registering ‘ocd_ps’…
Debug: 177 4 command.c:364 register_command_handler(): registering ‘ocd_test_mem_access’…
Debug: 178 4 ftdi.c:692 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 179 21 mpsse.c:422 mpsse_purge(): -
Debug: 180 21 mpsse.c:703 mpsse_loopback_config(): off
Debug: 181 21 mpsse.c:748 mpsse_set_frequency(): target 1000 Hz
Debug: 182 21 mpsse.c:740 mpsse_rtck_config(): off
Debug: 183 21 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 191 21 mpsse.c:709 mpsse_set_divisor(): 29999
Debug: 192 21 mpsse.c:772 mpsse_set_frequency(): actually 1000 Hz
Debug: 193 21 core.c:1712 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 194 21 core.c:1715 adapter_khz_to_speed(): have interface set up
Info : 195 21 core.c:1500 adapter_init(): clock speed 1 kHz
Debug: 196 21 openocd.c:135 handle_init_command(): Debug Adapter init complete
Debug: 197 21 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport init
Debug: 198 21 command.c:143 script_debug(): command - ocd_transport ocd_transport init
Debug: 200 21 transport.c:239 handle_transport_init(): handle_transport_init
Debug: 201 21 core.c:729 jtag_add_reset(): SRST line released
Debug: 202 21 core.c:753 jtag_add_reset(): TRST line released
Debug: 203 21 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 204 21 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init
Debug: 205 21 command.c:143 script_debug(): command - ocd_jtag ocd_jtag arp_init
Debug: 206 21 core.c:1513 jtag_init_inner(): Init JTAG chain
Debug: 207 21 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 208 21 core.c:1173 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 209 21 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 211 715 core.c:1072 jtag_examine_chain_display(): JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (), part: 0x0000, ver: 0x2)
Warn : 212 715 core.c:1072 jtag_examine_chain_display(): JTAG tap: riscv.cpu UNEXPECTED: 0x20000913 (mfg: 0x489 (), part: 0x0000, ver: 0x2)
Error: 213 715 core.c:1072 jtag_examine_chain_display(): JTAG tap: riscv.cpu expected 1 of 1: 0x10e31913 (mfg: 0x489 (), part: 0x0e31, ver: 0x1)
Error: 214 715 core.c:1558 jtag_init_inner(): Trying to use configured scan chain anyway…
Debug: 215 715 core.c:1304 jtag_validate_ircapture(): IR capture validation scan
Debug: 216 734 core.c:1362 jtag_validate_ircapture(): riscv.cpu: IR capture 0x01
Warn : 217 734 core.c:1581 jtag_init_inner(): Bypassing JTAG setup events due to errors
Debug: 218 734 openocd.c:148 handle_init_command(): Examining targets…
Debug: 219 734 target.c:1512 target_call_event_callbacks(): target event 21 (examine-start)
Debug: 220 734 riscv.c:327 riscv_examine(): riscv_examine()
Debug: 221 799 riscv.c:223 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x5071
Debug: 222 799 riscv.c:337 riscv_examine(): dtmcontrol=0x5071
Debug: 223 799 riscv.c:339 riscv_examine(): version=0x1
Debug: 224 799 riscv-013.c:643 init_target(): init
Debug: 225 865 riscv-013.c:280 dtmcontrol_scan(): DTMCS: 0x0 -> 0x5071
Debug: 226 866 riscv-013.c:966 examine(): dtmcontrol=0x5071
Debug: 227 866 riscv-013.c:967 examine(): dmireset=0
Debug: 228 866 riscv-013.c:968 examine(): idle=5
Debug: 229 866 riscv-013.c:969 examine(): dmistat=0
Debug: 230 866 riscv-013.c:970 examine(): abits=7
Debug: 231 866 riscv-013.c:971 examine(): version=1
Debug: 232 927 riscv-013.c:207 scan(): 41b r 00000000 @10 -> + 00000000 @00
Debug: 233 975 riscv-013.c:207 scan(): 41b - 00000000 @10 -> + 00000001 @10
Debug: 235 1036 riscv-013.c:207 scan(): 41b r 00000000 @11 -> + 00000000 @00
Debug: 236 1084 riscv-013.c:207 scan(): 41b - 00000000 @11 -> b 00000000 @00
Debug: 511 8630 riscv-013.c:207 scan(): 41b w 00000000 @2f -> + 00000000 @00
Debug: 512 8681 riscv-013.c:207 scan(): 41b - 00000000 @2f -> + 00000000 @2f
Debug: 513 8682 program.c:76 riscv_program_exec(): Executing program 0x7ffee9d74b20: debug_buffer[10] = DASM(0xffffffff)
Error: 519 9022 mpsse.c:909 mpsse_flush(): ftdi device did not return all data: 0, expected 6
Debug: 520 9022 mpsse.c:422 mpsse_purge(): -
Error: 521 9022 mpsse.c:430 mpsse_purge(): unable to purge ftdi rx buffers: LIBUSB_ERROR_NO_DEVICE
Error: 522 9022 ftdi.c:682 ftdi_execute_queue(): error while flushing MPSSE queue: -4
Error: 523 9022 riscv-013.c:347 dmi_scan(): dmi_scan failed jtag scan
Error: 524 9022 riscv-013.c:436 dmi_write(): failed write to 0x16, status=2

Error: 525 9022 riscv-013.c:443 dmi_write(): Failed write to 0x16;, status=2

Did I do anything wrong? (Note that some of the log is omitted here because there are too many “@”)

Thanks,
Dong


(Megan A. Wachs) #19

Well, what you are seeing is consistent if there is no core clock running. You can see that you can successfully access the DTM registers (clocked by TCK) but not the ones clocked by core clock (actually it looks even weirder, like perhaps reset was asserted?).

Have you figured out how to get your core clock running?


(SandSilicon) #21

I have ported Freedom E300 SoC for zybo broad successfully. If you’re interested in this, you can check my github repository: https://github.com/gongqingfeng/freedom_zybo.
Zybo is similar with ZedBoard. Both of them belong Zynq 7000 AP series. Therefore, I guess my repository may be helpful with you.


(Donnie Agema) #22

The github link appears to be brocken.


(SandSilicon) #23

I’m so sorry to give a wrong github link. I have edited it again and you can try this: https://github.com/gongqingfeng/freedom_zybo.