How much Freedom is autogenerated?

Hi All,

I’m starting to learn the Freedom’s source code and a thought occurred to me: how much of the Freedom source code was autogenerated from tools? And, if so, which tools?

Do documents exist that describe the source code in more detail, or how to play with it effectively on an Arty?

Thank you,

In this case, what specifically are you referring to when you say “Freedom source code?” Which code base?

Hi Jack,

I’m referring to I’m trying to grok the relationship between each SiFive variant and the RocketChip base, and how each variant builds from the RC core. So, I’m referring to the Scala sources and the Verilog code in each variant’s tree in that repository.

In other words, are the Scala and Verilog files that exist prior to running `make’ auto-generated through other tools, or are they hand written by the SiFive team?



All the Scala code in the Freedom repo is hand-written, though we laid down some basic conventions to make it easy to auto-generate in the future.

Some parts of the top-level system.v Verilog were generated with some simple in-house shell scripts. For example: But we don’t really consider that part of the flow, and we’re working to remove the top-level Verilog to avoid a separate scripting process outside of Chisel.

To answer the question you might be really asking about how Freedom uses Rocket-Chip… We view the Rocket Chip repo as an SoC Generator library, and our Freedom repo is the code which calls into that library to generate the Verilog for the different Freedom platform variants.

For example, to generate the Verilog to go onto the E300 Arty Dev Kit, the Makefile indicates the Top-level Chisel module is a E300ArtyDevKitTop :

E300ArtyDevKitTop instantiates an E300ArtyDevKitSystem:

E300ArtyDevKitSystem extends from the rocket-chip library’s BaseTop:



And to answer that question, have you checked out the Freedom E SDK ( and the Getting Started Guide:

Hi Megan,

Yeah, I have the E300 running successfully on my Arty and thanks to your other note (regarding the flash program env var) I can flash multiple apps onto the E300 image with my JLink Segger. So, I’m definitely up to speed on running the core itself and software on it.

I meant more are there details/docs regarding the E300 core and how it works in Chisel3. And by “playing with” I mean more altering the E300 image itself to play with the uC image’s features.

But, now that you’ve elaborate on how to read the Scala source code, I think I have a much better handle on how to read/interpret it. Very cool stuff here.