Getting Started modifying the E300 - generating RTL


(Paul Chaffey) #1

Hi All,

I have been through the SiFive-E310-arty-gettingstart.pdf and I have successfully loaded the Arty board with the demo. LED flashes as expected…

Next I have cloned freedom from the git repo, popped it onto a ubuntu VM and run the makefile:

make -f Makefile.e300artydevkit verilog

Everything has worked nicely I believe, and the file : sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v was generated in the …builds/e300artydevkit directory.

Now, being new to RISCV I would like to ask for advice on the next steps that I would take to experiment with slightly different cpu subsystems based directly on the E300. I have loads of RTL experience, but nothing in the Scala / RocketChip world. Pointers to manuals or even a physical book, and any next steps would be appreciated.

Many thanks, Paul.


(Paul Chaffey) #2

P.S. Can I assume that the RocketChip and Scala stuff is all in place as the “make” ran successfully. When I look into the README in the rocket-chip directory I see a load of extra dependencies required to build rocketchip from scratch. The “make” I ran above just seemed to pull in a load of pre-built jar files ?


#3

Hi Paul,

There is a learning curve with the scala/chisel code. in my opinion the directory to become familiar with is the src/main/scala/system files. Within the configs.scala you’ll see how the default processor that you generated via make is put together. There are also other example config in this file.

I found using "grep -r search-term * " extremely helpful when trying to see where each component in the config files was originally coded.

There is a wiki on the chisel3 page which has some useful information on how to get started: https://github.com/freechipsproject/chisel3/wiki

Also, there is an example workspace that is available to download: https://github.com/ucb-bar/chisel-template

The google group for riscv is also full or useful resources :
Hardware group: https://groups.google.com/a/groups.riscv.org/forum/#!forum/hw-dev
Software group : https://groups.google.com/a/groups.riscv.org/forum/#!forum/sw-dev

Hope this helps,
Ciaran


(Paul Chaffey) #4

Many thanks Ciaran - I will take a look…:grinning:


(Ânderson Ignacio da Silva) #5

Hello pchaffey,

I’m getting started too and I would like to ask you about which links have you been using to learn all this stuff? I also have experience with source RTL but none with scala/chisel3 languages…=/ One of things that I didn’t understand correctly yet is why SiFive team requires that you ask for the evaluation of the RTL if the freedom project in github has all the sources…Am I missing something? What’s the difference between this and rocketchip project?

Thanks!