I have a Freedom E300 ARTY FPGA Devkit. I am able to generate my own bitstream and run the examples from Freedom E SDK.
Right now, I am modifying the Chisel implementation of the core (Rocket Chip generator). For example, I am editing the Scala files in
When I regenerate the Verilog files,
make -f Makefile.e300artydevkit clean verilog
it generates a single 23MB file:
Q1. Is it possible to generate multiple Verilog files, e.g. one for the ALU, one for the decode stage, etc.? The suggested to use the
--split-modules flag for the FIRTTL invocation, but it did not work.
Q2. Can I attach an ILA in Vivado to monitor the core on the FPGA?
Q3. Can I co-simulate software / modified hardware (no FPGA)? [Edit: I assume I can do: https://github.com/freechipsproject/rocket-chip#emulator]