I have created the Verilog files for the Arty using the freedom package from Github. The make ran without problems, but when I try to create and synthesize an RTL probject in Vivado, it is not recognizing modules declared in the generated FIRRTL file. I do not know how to handle FIRRTL files in Vivado, and all of the links I find in the web are in chinese (I am guessing).
Can anyone point me to some relevant documentation?
Donnie,
The FIRRTL file is an intermediate format, from which the Verilog is generated. You should not need to use FIRRTL file.
The files you are missing are those that are written in Verilog instead of generated from Chisel. See the Makefile for the Dev Kit:
EXTRA_FPGA_VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/DebugTransportModuleJtag.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v
So you can find them in either freedom/sifive-blocks/vsrc and freedom/rocket-chip/vsrc.
Hi Megan,
I added both directories to the Vivado project, deactivated the files TestDriver.v and SimDTM.v, and now the synthesis is running without errors.
Thank you very much!
The design elaboration and synthesis ran without errors, but the implementation fails because the Arty has only 210 I/O ports and the circuit contains 284 I/O ports. It looks like I must remove at least 74 I/O port from the circuit, but I cannot identify the ones which can most likely be removed without getting into other problems. The highest numbered GPIO pads maybe?
There is also a top level verilog file:
freedom/fpga/e300artydevkit/src
Adding system.v (the only file contained in freedom/fpga/e300artydevkit/src) had no effect on the I/O error. Assigning it as the Top file also had no effect. The design still contains 284 I/O ports.
±----------------------------±-----±------±----------±-------+
| Site Type | Used | Fixed | Available | Util% |
±----------------------------±-----±------±----------±-------+
| Bonded IOB | 278 | 0 | 210 | 132.38 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| ILOGIC | 0 | 0 | 210 | 0.00 |
| OLOGIC | 0 | 0 | 210 | 0.00 |
±----------------------------±-----±------±----------±-------+
Hmm… did you also apply the XDC constraints files in freedom/fpga/e300artydevkit/constrs/ ?
Ah… That is what was missing. I arbitrarily removed gpio pads 17 thru 31 and was able to implement, but there were no pin assignments to the remaining 188 pads. I was just about to ask where to find the contraints (fortune favours those who can read 
).
Thanks again!
Oh and one additional question, if I may. I am not familar with Verilog. How would I have to go about generating VHDL out of Chisel instead of Verilog? Sorry, I am having to learn so many new tricks, it is not so easy for an old dog. I would like to avoid having to learn Verilog if possible.
What’s the utilisation like on LUTs/slices etc? Curious how much space is spare. Could two cores be implemented in the Arty?
That was the first thiing I also wanted to know. The synthesis with correct contrtaint files is still running, so the numbers might change to the positive, but the implementation after having deleted gpio pads 17 thru 31 showed showed 60% utilization of LUTs and 90% utilization of I/O ports. All other values were in the lower teens and twens. I`ll give an update as soon as the new implementation is finished.
Would also love to know how long the various steps take, in Chisel, synthesis, loading into the FPGA … whatever else is needed. And the specs of your PC 
After rerverting my gpio pad deletions from the circuit and integrating the XDC constraint files, I once again get 284 utilized I/O ports and thus cannot implement.
Donnie, can you show the exact error message? Perhaps it is still inferring the wrong top level somehow.
I am running Vivado under Windows on a Lenovo laptop
and Ubunto 16.04. on a virtual machine
Synthesis in Vivado takes abiout 18 minutes:
synth_design: Time (s): cpu = 00:17:42 ; elapsed = 00:17:54 . Memory (MB): peak = 1688.258 ; gain = 1475.910
I have not yet been able to implement successfully, so I cannot report how long implementation or bitfile generation and upload takes.
I can’t give an exact time for the make in Chisel, but as I recall it took a few or more hours.May have completed faster had I run it with parallel jobs parameter.
Hmm. N3540 looks like about 1000 - 1100 per core on Geekbench3. So 40% the speed of my i7-2720QM MacBook Pro, or 20% the speed of my i7-6700K Linux desktop.
So synthesis times should be reasonable here.
I guess there’s nothing to stop me trying Chisel without an Arty.
Yeah, but I still love it for its absolute noiselessness. 
I banned my power PCs to the washroom where they can make all the noise they want. When I do serious compute work, I connect and run there remote.
I also see that it is not finding the generated IP. You will need to generate the IP so you can use it (this is for the clock generation block and the System Reset block. In the freedom flow, this is done by a TCL script:
https://github.com/sifive/freedom/blob/master/fpga/e300artydevkit/script/ip.tcl
In the screenshot, It has ‘dut’ is bolded, which makes me think that it is still trying to use E300ArtyDevKitTop as the Top-level. Make sure that “system.v” is selected as the top for the entire synthesis/placement flow.
Sure. My machine for that stuff is a MacBook Air. Can’t even notice the speed difference with web browsing, spreadsheets etc. Notice a BIG difference building things such as the freedom-e-sdk, which is almost five minutes on my big machine. It could well be an hour on the Air.
Big tower PCs don’t have to be noisy. It’s surprisingly few extra dollars to spec them with cases with thicker walls, insulation, bigger and better and slower fans. Very hard to find pre-built though.
