The E310 and Vivado (in GUI mode)


(Sean) #1

The E310 Getting Started Guide has a short section on using Xilinx Vivado to load the MCS file. I would like to add some “homemade” hardware blocks to the design. Is there any documentation on how to use Vivado to take a design from start to finish using the GUI? Ideally I would love to see an example of the steps taken in Vivado: adding the sources, setting the constraints (ie, mapping the core pins to the FPGA pins), synthesizing, implementing, and generating the bitstream.

Alternately, I know that I can run the Makefile from https://github.com/sifive/freedom to achieve the same thing, but there are a couple of steps that are eluding me. For example, how does the pin mapping from the E3 Core Complex pins to the FPGA happen? I have been dissecting the Makefile, but it’s slow going and not all of the steps are clear to me.

Any help/advice would be appreciated!


(HORIE Tetsuya) #2

Alternately, I know that I can run the Makefile from https://github.com/sifive/freedom to achieve the same thing, but there are a couple of steps that are eluding me. For example, how does the pin mapping from the E3 Core Complex pins to the FPGA happen?

I ported “The Freedom E310 Arty FPGA Dev Kit” to Nexys4 DDR on following my forked project.

Then, I connected 7 Segment LED module, VGA, added Block RAM for VRAM.

If you look commit log, you may dissect how to map the pin.


(Bruce Hoult) #3

This is great!

If you or anyone else has the time and knowledge to also make it work on other boards such as ZedBoard, Basys3, Arty Z7, Arty S7 … or even just the Arty A7-100 that would be really great. Or other manufacturers boards.


(Sean) #4

Hi HORIE_Tetsuya, thanks for the input. I will take a look at your forked repository this afternoon!


(Michael Wildoer) #5

You might also like to check out my blog on an open Arty RISC-V computer I’m developing called the ‘ArtyRV board’ (see http://lavaworkshop.tumblr.com). It’s intended for education and experimentation.

In this project, the RISC-V core is fully open, so you can check out the core’s VHDL code. It runs on Vivado, linked to the Artix-7 35T Arty FPGA Evaluation Kit. The project is currently in development, but will be available for download in beta form fairly soon (I’m still finishing the IDE). The download will include the Vivado 2018.1 project files.

I think you’ll really like the blog, as it explains everything as simply as possible, but thoroughly as well.

Blog sections include:

  • Summary
  • Introduction
  • Finding a RISC-V core for the Arty
  • Getting the RISC-V core running
  • Designing a VGA video controller
  • The beauty of bare metal RISC-V
  • An interactive RISC-V disassembler
  • Programming the ArtyRV board in C
  • RVStudio gets a powerful IDE
  • Where do we go from here?

(Sean) #6

Hi Michael, thanks for the information. I will take a look at the blog this afternoon!


(Sean) #7

Hi Tesuya_san (and please correct me if I am not using the name and/or honorific correctly), I have looked at your repository. It looks like you have done excellent work porting the rocket chip to the Nexys 4. If I get a Nexys 4 board, I will definitely try your repository. In the meantime, I am looking at your files to better understand how to work with the rocket chip and the platform files. Thanks again for giving me the link to the repository.

Hi Michael, I have looked at your blog and look forward to the release of the files. After I have digested the blog in more detail, I will probably have some questions for you if that is OK.


(SandSilicon) #8

I have ported Freedom E300 SoC for zybo broad successfully. If you’re interested in this, you can check my github repository: https://github.com/gongqingfeng/freedom_zybo.
Zybo is similar with ZedBoard. Both of them belong Zynq 7000 AP series.


(Donnie Agema) #9

Can you check the github link? It appears to be brocken/non-existent.