RTL core Simulation


(cyril) #1

Hi all,

I am a student and very interested in learning RISC-V core. I am currently working on the implementation of fpga freedom e300. The synthesis on arty works perfectly and I can run code without problems. Now wishing to modify the architecture I am looking for a way to simulate the architecture and observe the different signals and/or generate a vcd file. Is there a documentation or a way to do this?

thank you very much for your answer