I started an Simulation of the e300 Design in Vivado. Therefore a connected an clock to CLK100MHZ and set ck_rst to 1. All of the other ports of the E300ArtyDevKitFPGAChip instantiation were left open.
When I start the simulation I can see that the rom is initialized with the xpr instructions, but the core doesn’t start to read out of it (the port ‘me’ is always 0).
Could someone tell me if there is the need of some other ports to be connected to 1 or to 0?
Further I am not sure which defines have to be made for the correct function of the testbench. This are the defines that I tried:
`timescale 1ns / 1ps `define RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE_INVALID_ASSIGN `define RANDOMIZE_REG_INIT `define RANDOMIZE_MEM_INIT `define RANDOMIZE_DELAY 0.000002 `define INIT_RANDOM `define RANDOM 0
I am using the Vivado Simulator and I also tried Aldec to run the simulation.