E300 Simulation doesn't start Execution

I started an Simulation of the e300 Design in Vivado. Therefore a connected an clock to CLK100MHZ and set ck_rst to 1. All of the other ports of the E300ArtyDevKitFPGAChip instantiation were left open.

When I start the simulation I can see that the rom is initialized with the xpr instructions, but the core doesn’t start to read out of it (the port ‘me’ is always 0).

Could someone tell me if there is the need of some other ports to be connected to 1 or to 0?

Further I am not sure which defines have to be made for the correct function of the testbench. This are the defines that I tried:

`timescale 1ns / 1ps
`define RANDOMIZE_DELAY 0.000002
`define RANDOM 0 

I am using the Vivado Simulator and I also tried Aldec to run the simulation.

Solved: The problem was that I had to wait for the RTC Timer to wake the core up, so I had to simulate for a realy long time