Before explaining what is the issue. I would like to mention that RTL simulation and FPGA test work perfectly. The problem is actually simulating the synthesized netlist.
In RTL simulation there is this function $random to initialize the registers and the memory. It also can be replaced with +vcs+initreg and +vcs+initmem. First we can agree that RTL simulation wouldn’t work if RANDOMIZE_REG_INIT is not defined. This is because in the “always” blocks not all registers are initialized on the reset.
Now the problem is that $random is not synthesizable and this leaves the registers not initialized in the netlist. In addition to that the standard cells of the fab I am using do not contain “reg” structure. This means that +vcs+initreg has no effect on these gates. The observable result is many unknown state registers at the start and late triggered reset signals leading to a failure of operation.
I am guessing that the operation is normal on an FPGA because in real circuit the unknown state does not exist and that registers do have at least 0 value before the start of the operation.
I am thinking to modify the generated RTL by initializing the registers that are not initialized at the rising edge of the reset signal. Is it advisable or is there a better way.