RTL simulation under verdi/VCS

Hello guys
I git the freedom source and make verilog according to the README, which generates a huge .v file and various others.

I have three questions:
First, is the generated verilog specified for VC707 board?
Second, what’s the purpose of the files other than the .v?
Finally, there are undefined modules in the .v file which cause some syntax errors, such as vc707mig, vc707axi_to_pcie_x1, ibufds_gte2 etc. Are those definitions contained within the project or protected IP? How do we generate them if they’re IPCores?
Many thanks

First, yes
Second,they are intermidate file for verilog generation
Finally, you need found them from xilinx sim model,

To elaborate on what the other generated files are (I updated your list with the outputs from the newest version of the repo):

.d : Makefile snippet for test flows

.dts: Device Tree description of the SoC.

.fir : This is the FIRRTL file. The Chisel code generates FIRRTL code, then firrtl generates the Verilog. You can learn about firrtl here: https://github.com/freechipsproject/firrtl

.graphml : This is a file which represents the connectivity of the design. It can be opened in a graphml viewer like yEd (http://www.yworks.com/products/yed?). It does not show the entire module hierarchy, just things like Buses and interrupts.

.json: Easy to parse versions of information about the SoC, useful for software flows.

.rom.conf: Description of the ROM Macros found in the design (used by another step to create the Boot ROM verilog with the code included)

To generate the necessary IP Cores, you will need the proper licensed version of Vivado which can handle VC707. Then there are IP generation scripts in the fpga-shells/xilinx/vc707/tcl/ directory.

Apologies for late reply.
Guys here say the SoC can be burned into unofficial board like U500 on Arty, for economic concerns. The IP Core license seems counterproductive. Is vendor independent code currently available?
Thanks very much