I git the freedom source and make verilog according to the README, which generates a huge .v file and various others.
I have three questions:
First, is the generated verilog specified for VC707 board?
Second, what’s the purpose of the files other than the .v?
Finally, there are undefined modules in the .v file which cause some syntax errors, such as vc707mig, vc707axi_to_pcie_x1, ibufds_gte2 etc. Are those definitions contained within the project or protected IP? How do we generate them if they’re IPCores?