Information on Coreplex IP Access

[dsb]

Hi Sir/Madam,

I have searched through the Coreplex series documentation available on dev.sifive.com

I wanted to find out if Verilog of Coreplex is available for developers to prototype and build. If yes, please point to this resource.

Thanks,
Santosh

[Krste (Krste Asanovic)]

At SiFive, all RTL development is done in Chisel as we find this the most productive way to build and maintain a powerful chip generation system. We open-source our Chisel generators and support these via our developer forums. The community is free to generate Verilog from our Chisel code, and then redistribute the generated Verilog for others to use. However, SiFive cannot support generated Verilog instances alongside our Chisel code base. UC Berkeley had a brief experiment with providing V-Scale, a Verilog version of Z-scale, but it was too difficult to track changes in the upstream Rocket-Chip code base and V-scale soon became out of date. SiFive has a separate Coreplex product line that provides customized and supported soft Verilog IP for customers who wish to pay for this service for a particular project.

[dagema (Donnie Agema)]

@Krste

At SiFive, all RTL development is done in Chisel as we find this the most productive way to build and maintain a powerful chip generation system. We open-source our Chisel generators and support these via our developer forums. The community is free to generate Verilog from our Chisel code, and then redistribute the generated Verilog for others to use

I have tried both Chisel and Chisel3, but in each case, the chisel-tutorial “Getting Started with Chisel” document https://chisel.eecs.berkeley.edu/2.2.0/chisel-getting-started.pdf does not reflect a directory structure that anyway near resembles the structure actually contained in the GitHub repository. Can someone point me to a getting started document which is up to date/in sync with the repository?

[dagema (Donnie Agema)]

@dagema

have tried both Chisel and Chisel3, but in each case, the chisel-tutorial “Getting Started with Chisel” document https://chisel.eecs.berkeley.edu/2.2.0/chisel-getting-started.pdf does not reflect a directory structure that anyway near resembles the structure actually contained in the GitHub repository. Can someone point me to a getting started document which is up to date/in sync with the repository?

Ok, I found what I was looking for here - by ingnoring the content of the GitHub chisel-tutorial readme and jump directly to the wiki (NOT the Chisel3 wiki). This document matches the GitHub repository and I am able to get through the instruction without problems.

[renau (Jose Renau)]

DDR coreplex IP

The Freedom U500 VC707 has a DDR3/4 controller according to the specification, but I was not able to see the code in the rocket repo. A search in the github rocket-chip repo show no hits for DDR

chipsalliance/rocket-chip

Is the DDR controller code available?

[terpstra (Wesley W. Terpstra)]

In sifive-blocks you will find the code to use the Xilinx MIG, which is a DDR controller.

[Pranav (Pranav Gadre)]

@Krste

At SiFive, all RTL development is done in Chisel as we find this the most productive way to build and maintain a powerful chip generation system.

Sir, are there other HDLs being used at SiFive besides Chisel as of now (2020)?

[Krste (Krste Asanovic)]

Chisel is still the main HDL used at SiFive to write our own IP. Some smaller components are developed directly in Verilog where convenient, and we have to deal with third-party IP written predominantly in Verilog.

[Pranav (Pranav Gadre)]

Sir, Thank you so much for this useful information. It is such a Huge Privilege for me to get the first ever reply from you.