At SiFive, all RTL development is done in Chisel as we find this the most productive way to build and maintain a powerful chip generation system. We open-source our Chisel generators and support these via our developer forums. The community is free to generate Verilog from our Chisel code, and then redistribute the generated Verilog for others to use. However, SiFive cannot support generated Verilog instances alongside our Chisel code base. UC Berkeley had a brief experiment with providing V-Scale, a Verilog version of Z-scale, but it was too difficult to track changes in the upstream Rocket-Chip code base and V-scale soon became out of date. SiFive has a separate Coreplex product line that provides customized and supported soft Verilog IP for customers who wish to pay for this service for a particular project.