Freedom E300 RTL Synthesis in Artix-7 AC701

I am a student . I have generated the SiFive Freedom E300 RTL Verilog code with Ubuntu and copy the source code to Centos 7, where my Vivado is installed. But when I generate the bitstream with Vivado and program the Artix-7 AC701, the UART does not display the SiFive message it should display in the serial communication terminal. I am looking for a possible solution.