Timing issue, u500 on v2000T custom board


(Anup Kini) #1

Dear Team,

I am trying to build u500 on a custom v2000T board.
I was able to port the mig flow and commented out PCIe and Ethernet for the time being.

During Place and Route, I get a lot hold violations and unable to figure out how to proceed.
The issue is seen mainly in the MIG Island, where async queue is used to match between the dut clock and mig’s axi clock.

Slack (VIOLATED) : -4.272ns (required time - arrival time)
Source:
xilinxv2000Tmig_1/island/AXI4AsyncCrossingSink/AsyncQueueSource/mem_1_data_reg[48]/C
(rising edge-triggered cell FDRE clocked by clk_pll_i_1 {rise@0.000ns fall@5.000ns period=10.000ns})

Destination: U500V2000TSystem/xilinxv2000Tmig_1/AXI4AsyncCrossingSource/AsyncQueueSink/deq_bits_reg/sync_0_reg[51]/D
(rising edge-triggered cell FDRE clocked by clk_out4_v2000T_sys_clock_mmcm0 {rise@0.000ns fall@10.000ns period=20.000ns})

Kindly let me know if you have faced something similar while building for vc707.

Thanks,
Anup.


(Anup Kini) #2

Hi Guys,

With some searching and using report_cdc, I found that the constraints were incorrect for while setting async groups.
The timing issues are resolved and I could generate the bitstream.

Thanks.
Anup.