I try to compile the code from https://github.com/sifive/freedom using latest Xilinx Vivado design suite. However, I got timing violation after implementation. Any suggestion? The report is as follows:
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
| Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
| Date : Thu Jan 12 22:17:18 2017
| Host : localhost.localdomain running 64-bit CentOS Linux release 7.3.1611 (Core)
| Command : report_timing_summary -file /home/rvdev/rv/sifive/freedom/fpga/e300artydevkit/obj/report/timing.txt -max_paths 10
| Design : system
| Device : 7a35ti-csg324
| Speed File : -1L PRODUCTION 1.16 2016-11-09 |
|---|
…
| Design Timing Summary |
|---|
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-3.545 -3237.531 2388 18514 0.054 0.000 0 18514 3.000 0.000 0 7832
Timing constraints are not met.
…
Max Delay Paths
Slack (VIOLATED) : -3.545ns (required time - arrival time)
Source: dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/T_78_reg/C
(rising edge-triggered cell FDRE clocked by clk_out2_mmcm {rise@0.000ns fall@7.695ns period=15.391ns})
Destination: dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_1463_0_lut_reg[3]/S
(rising edge-triggered cell FDSE clocked by clk_out2_mmcm {rise@0.000ns fall@7.695ns period=15.391ns})
Path Group: clk_out2_mmcm
Path Type: Setup (Max at Slow Process Corner)
Requirement: 15.391ns (clk_out2_mmcm rise@15.391ns - clk_out2_mmcm rise@0.000ns)
Data Path Delay: 18.340ns (logic 5.080ns (27.699%) route 13.260ns (72.301%))
Logic Levels: 28 (CARRY4=2 LUT1=1 LUT3=2 LUT4=4 LUT5=5 LUT6=13 RAMD32=1)
Clock Path Skew: -0.025ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.447ns = ( 13.944 - 15.391 )
Source Clock Delay (SCD): -0.845ns
Clock Pessimism Removal (CPR): 0.577ns
Clock Uncertainty: 0.142ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.275ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
(clock clk_out2_mmcm rise edge)
0.000 0.000 r
E3 0.000 0.000 r CLK100MHZ (IN)
net (fo=0) 0.000 0.000 ip_mmcm/inst/clk_in1
E3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r ip_mmcm/inst/clkin1_ibufg/O
net (fo=1, routed) 1.233 2.722 ip_mmcm/inst/clk_in1_mmcm
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
-6.946 -4.224 r ip_mmcm/inst/mmcm_adv_inst/CLKOUT1
net (fo=1, routed) 1.661 -2.563 ip_mmcm/inst/clk_out2_mmcm
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.467 r ip_mmcm/inst/clkout2_buf/O
net (fo=7790, routed) 1.622 -0.845 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/clk_out2
SLICE_X7Y51 FDRE r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/T_78_reg/C
SLICE_X7Y51 FDRE (Prop_fdre_C_Q) 0.456 -0.389 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/T_78_reg/Q
net (fo=102, routed) 1.071 0.682 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/ram_address_reg_0_1_30_31/ADDRA0
SLICE_X6Y54 RAMD32 (Prop_ramd32_RADR0_O)
0.124 0.806 f dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/ram_address_reg_0_1_30_31/RAMA_D1/O
net (fo=10, routed) 0.701 1.507 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/ram_address_T_107_data[31]
SLICE_X6Y49 LUT1 (Prop_lut1_I0_O) 0.124 1.631 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/T_1463_0_fifoId[0]_i_2/O
net (fo=1, routed) 0.000 1.631 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/T_1463_0_fifoId[0]_i_2_n_0
SLICE_X6Y49 CARRY4 (Prop_carry4_S[1]_CO[1])
0.492 2.123 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/T_1463_0_fifoId_reg[0]_i_1/CO[1]
net (fo=3, routed) 0.428 2.551 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_78_reg_7[0]
SLICE_X5Y50 LUT6 (Prop_lut6_I1_O) 0.332 2.883 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/saved_opcode[2]_i_7__1/O
net (fo=4, routed) 0.477 3.359 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/saved_opcode[2]_i_7__1_n_0
SLICE_X4Y53 LUT6 (Prop_lut6_I0_O) 0.124 3.483 f dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/acq_address[31]_i_2/O
net (fo=140, routed) 0.854 4.337 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_2154_1
SLICE_X2Y53 LUT4 (Prop_lut4_I1_O) 0.124 4.461 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/saved_opcode[2]_i_5__8/O
net (fo=1, routed) 0.000 4.461 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/saved_opcode[2]_i_5__8_n_0
SLICE_X2Y53 CARRY4 (Prop_carry4_S[1]_CO[1])
0.492 4.953 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/saved_opcode_reg[2]_i_3__6/CO[1]
net (fo=12, routed) 0.617 5.570 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/CO[0]
SLICE_X7Y54 LUT5 (Prop_lut5_I3_O) 0.332 5.902 f dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/ram_data_reg_0_1_0_5_i_16__0/O
net (fo=3, routed) 0.458 6.360 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_1491_0_data_reg[0]_2
SLICE_X7Y54 LUT5 (Prop_lut5_I0_O) 0.124 6.484 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/ram_size_reg_0_1_0_2_i_7__0/O
net (fo=42, routed) 0.943 7.427 dut/E300ArtyDevKitSystem_1/coreplex/plic_TLFragmenter/repeater/T_7103_1_reg_0
SLICE_X8Y52 LUT5 (Prop_lut5_I0_O) 0.124 7.551 r dut/E300ArtyDevKitSystem_1/coreplex/plic_TLFragmenter/repeater/ram_source_reg_0_1_1_1_i_3__1/O
net (fo=3, routed) 0.427 7.979 dut/E300ArtyDevKitSystem_1/coreplex/clint_TLFragmenter/repeater/saved_source_reg[1]_0
SLICE_X9Y52 LUT5 (Prop_lut5_I1_O) 0.124 8.103 r dut/E300ArtyDevKitSystem_1/coreplex/clint_TLFragmenter/repeater/ram_source_reg_0_1_1_1_i_1__2/O
net (fo=4, routed) 0.596 8.698 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/io_enq_bits_source[1]
SLICE_X10Y52 LUT6 (Prop_lut6_I1_O) 0.124 8.822 f dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/ram_data_reg_0_1_0_5_i_10__0/O
net (fo=6, routed) 0.352 9.174 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_12_1/T_76_reg
SLICE_X11Y52 LUT6 (Prop_lut6_I2_O) 0.124 9.298 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_12_1/saved_opcode[2]_i_3__1/O
net (fo=10, routed) 0.337 9.636 dut/E300ArtyDevKitSystem_1/coreplex/cbus/T_85_reg
SLICE_X11Y54 LUT6 (Prop_lut6_I0_O) 0.124 9.760 f dut/E300ArtyDevKitSystem_1/coreplex/cbus/state[0]_i_4__1/O
net (fo=1, routed) 0.292 10.052 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/cbus_io_out_3_d_ready
SLICE_X11Y55 LUT6 (Prop_lut6_I0_O) 0.124 10.176 f dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/state[0]_i_3/O
net (fo=3, routed) 0.166 10.342 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/state[0]_i_3_n_0
SLICE_X11Y55 LUT4 (Prop_lut4_I0_O) 0.124 10.466 f dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/i___28_i_1/O
net (fo=10, routed) 0.313 10.779 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/T_1446
SLICE_X11Y55 LUT5 (Prop_lut5_I0_O) 0.124 10.903 r dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/i___28/O
net (fo=50, routed) 0.565 11.468 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/i___28_n_0
SLICE_X10Y58 LUT6 (Prop_lut6_I1_O) 0.124 11.592 r dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/s1_req_cmd[2]_i_1/O
net (fo=2, routed) 0.682 12.274 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/ScratchpadSlavePort_1/ex_ctrl_mem_cmd_reg[3][1]
SLICE_X10Y58 LUT6 (Prop_lut6_I3_O) 0.124 12.398 f dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/ScratchpadSlavePort_1/s1_valid_i_5/O
net (fo=3, routed) 0.185 12.583 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/core/ex_ctrl_mem_cmd_reg[0]_0
SLICE_X10Y58 LUT4 (Prop_lut4_I3_O) 0.124 12.707 f dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/core/blockUncachedGrant_i_4/O
net (fo=1, routed) 0.165 12.872 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/dcache/data/ex_ctrl_mem_reg
SLICE_X10Y58 LUT6 (Prop_lut6_I4_O) 0.124 12.996 r dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/dcache/data/pstore2_valid_i_3/O
net (fo=5, routed) 0.355 13.351 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/dcache/data/pstore2_storegen_data_reg[0]
SLICE_X9Y58 LUT6 (Prop_lut6_I0_O) 0.124 13.475 r dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/dcache/data/T_287_0_reg_i_38/O
net (fo=2, routed) 0.418 13.893 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/dcache/T_287_0_reg
SLICE_X9Y58 LUT4 (Prop_lut4_I0_O) 0.124 14.017 r dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/dcache/s1_valid_i_4/O
net (fo=1, routed) 0.452 14.469 dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/dcache/s1_valid_i_4_n_0
SLICE_X9Y57 LUT6 (Prop_lut6_I0_O) 0.124 14.593 r dut/E300ArtyDevKitSystem_1/coreplex/RocketTile_1/dcache/s1_valid_i_3/O
net (fo=9, routed) 0.617 15.210 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/dcache_io_cpu_req_ready_alias
SLICE_X9Y55 LUT3 (Prop_lut3_I0_O) 0.124 15.334 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_1463_0_bits_opcode[0]_i_7_rewire/O
net (fo=1, routed) 0.599 15.933 dut/E300ArtyDevKitSystem_1/coreplex/cbus/state_reg[0]
SLICE_X6Y52 LUT6 (Prop_lut6_I3_O) 0.124 16.057 r dut/E300ArtyDevKitSystem_1/coreplex/cbus/T_1463_0_bits_opcode[0]_i_2/O
net (fo=11, routed) 0.235 16.292 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/cbus_io_in_0_a_ready
SLICE_X6Y52 LUT6 (Prop_lut6_I4_O) 0.124 16.416 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_1463_0_bits_opcode[0]_i_1/O
net (fo=6, routed) 0.464 16.880 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/T_1422_0_state
SLICE_X6Y52 LUT3 (Prop_lut3_I0_O) 0.124 17.004 r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLBuffer/Queue_11_1/T_1463_0_lut[3]_i_1__0/O
net (fo=1, routed) 0.491 17.495 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/SS[0]
SLICE_X7Y50 FDSE r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_1463_0_lut_reg[3]/S
(clock clk_out2_mmcm rise edge)
15.391 15.391 r
E3 0.000 15.391 r CLK100MHZ (IN)
net (fo=0) 0.000 15.391 ip_mmcm/inst/clk_in1
E3 IBUF (Prop_ibuf_I_O) 1.418 16.809 r ip_mmcm/inst/clkin1_ibufg/O
net (fo=1, routed) 1.162 17.971 ip_mmcm/inst/clk_in1_mmcm
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
-7.204 10.767 r ip_mmcm/inst/mmcm_adv_inst/CLKOUT1
net (fo=1, routed) 1.581 12.348 ip_mmcm/inst/clk_out2_mmcm
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 12.439 r ip_mmcm/inst/clkout2_buf/O
net (fo=7790, routed) 1.505 13.944 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/clk_out2
SLICE_X7Y50 FDSE r dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_1463_0_lut_reg[3]/C
clock pessimism 0.577 14.521
clock uncertainty -0.142 14.379
SLICE_X7Y50 FDSE (Setup_fdse_C_S) -0.429 13.950 dut/E300ArtyDevKitSystem_1/coreplex/cbus_TLAtomicAutomata/T_1463_0_lut_reg[3]
required time 13.950
arrival time -17.495
slack -3.545
…
