Hi,
When I change TL_CLK of vcu118 to 200 MHz, the compilation fails. The following is printed information and part of file timing.txt. Thank you very much.
report_io: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.75 . Memory (MB): peak = 10417.094 ; gain = 0.000 ; free physical = 323348 ; free virtual = 739198
report_clocks -file [file join $rptdir clocks.txt]
set timing_slack [get_property SLACK [get_timing_paths]]
if {$timing_slack < 0} {
puts “Failed to meet timing by $timing_slack, see [file join $rptdir timing.txt]”
exit 1
}
Failed to meet timing by -0.263, see /vc707_nopci/freedom/builds/vcu118-u500devkit/obj/report/timing.txt
INFO: [Common 17-206] Exiting Vivado at Mon Apr 13 12:37:05 2020…
common.mk:81: recipe for target ‘/vc707_nopci/freedom/builds/vcu118-u500devkit/obj/VCU118Shell.bit’ failed
make: *** [/vc707_nopci/freedom/builds/vcu118-u500devkit/obj/VCU118Shell.bit] Error 1
From Clock: clk_out1_corePLL
To Clock: clk_out1_corePLL
Setup : 5698 Failing Endpoints, Worst Slack -0.263ns, Total Violation -577.724ns
Hold : 0 Failing Endpoints, Worst Slack 0.004ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 1.062ns, Total Violation 0.000ns
Max Delay Paths
Slack (VIOLATED) : -0.263ns (required time - arrival time)
Source: topDesign/topMod/tile_2/fpuOpt/dfma/in_in2_reg[63]_replica/C
(rising edge-triggered cell FDSE clocked by clk_out1_corePLL {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[105]/D
(rising edge-triggered cell FDRE clocked by clk_out1_corePLL {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_out1_corePLL
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (clk_out1_corePLL rise@5.000ns - clk_out1_corePLL rise@0.000ns)
Data Path Delay: 5.250ns (logic 3.783ns (72.057%) route 1.467ns (27.943%))
Logic Levels: 23 (CARRY8=9 DSP_A_B_DATA=1 DSP_ALU=3 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=3 DSP_PREADD_DATA=1 LUT3=2 LUT4=1 LUT6=1)
Clock Path Skew: 0.088ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.440ns = ( 10.440 - 5.000 )
Source Clock Delay (SCD): 5.115ns
Clock Pessimism Removal (CPR): -0.237ns
Clock Uncertainty: 0.127ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.243ns
Phase Error (PE): 0.000ns
Clock Net Delay (Source): 3.036ns (routing 1.411ns, distribution 1.625ns)
Clock Net Delay (Destination): 2.902ns (routing 1.282ns, distribution 1.620ns)
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
(clock clk_out1_corePLL rise edge)
0.000 0.000 r
E12 0.000 0.000 r sys_clock_p (IN)
net (fo=0) 0.000 0.000 sys_clock_ibufds/I
HPIOBDIFFINBUF_X1Y300
DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
0.530 0.530 r sys_clock_ibufds/DIFFINBUF_INST/O
net (fo=1, routed) 0.050 0.580 sys_clock_ibufds/OUT
E12 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
0.000 0.580 r sys_clock_ibufds/IBUFCTRL_INST/O
net (fo=1, routed) 0.335 0.915 corePLL_clk_in1
BUFGCE_X1Y289 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.028 0.943 r corePLL_clk_in1_BUFG_inst/O
net (fo=20, routed) 0.991 1.934 corePLL/inst/clk_in1
MMCM_X1Y11 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
-0.127 1.807 r corePLL/inst/mmcme4_adv_inst/CLKOUT0
net (fo=1, routed) 0.244 2.051 corePLL/inst/clk_out1_corePLL
BUFGCE_X1Y266 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.028 2.079 r corePLL/inst/clkout1_buf/O
X3Y8 (CLOCK_ROOT) net (fo=62108, routed) 3.036 5.115 topDesign/topMod/tile_2/fpuOpt/dfma/clk_out1
SLR Crossing[2->1]
SLICE_X60Y353 FDSE r topDesign/topMod/tile_2/fpuOpt/dfma/in_in2_reg[63]_replica/C
SLICE_X60Y353 FDSE (Prop_EFF_SLICEM_C_Q)
0.076 5.191 f topDesign/topMod/tile_2/fpuOpt/dfma/in_in2_reg[63]_replica/Q
net (fo=1, routed) 0.096 5.287 topDesign/topMod/tile_2/fpuOpt/dfma/fma/in_in2_reg_n_0_[63]_repN_alias
SLICE_X60Y353 LUT3 (Prop_B6LUT_SLICEM_I0_O)
0.089 5.376 f topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14_i_19__1/O
net (fo=3, routed) 0.135 5.511 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/A[18]
DSP48E2_X8Y141 DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[18]_A2_DATA[18])
0.192 5.703 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_A_B_DATA_INST/A2_DATA[18]
net (fo=1, routed) 0.000 5.703 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_A_B_DATA.A2_DATA<18>
DSP48E2_X8Y141 DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[18]_A2A1[18])
0.076 5.779 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_PREADD_DATA_INST/A2A1[18]
net (fo=1, routed) 0.000 5.779 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_PREADD_DATA.A2A1<18>
DSP48E2_X8Y141 DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[18]_U[38])
0.505 6.284 f topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_MULTIPLIER_INST/U[38]
net (fo=1, routed) 0.000 6.284 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_MULTIPLIER.U<38>
DSP48E2_X8Y141 DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[38]_U_DATA[38])
0.047 6.331 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_M_DATA_INST/U_DATA[38]
net (fo=1, routed) 0.000 6.331 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_M_DATA.U_DATA<38>
DSP48E2_X8Y141 DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[38]_ALU_OUT[47])
0.585 6.916 f topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_ALU_INST/ALU_OUT[47]
net (fo=1, routed) 0.000 6.916 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_ALU.ALU_OUT<47>
DSP48E2_X8Y141 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[47]_PCOUT[47])
0.122 7.038 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__2/DSP_OUTPUT_INST/PCOUT[47]
net (fo=1, routed) 0.038 7.076 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__3/PCIN[47]
DSP48E2_X8Y142 DSP_ALU (Prop_DSP_ALU_DSP48E2_PCIN[47]_ALU_OUT[47])
0.546 7.622 f topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__3/DSP_ALU_INST/ALU_OUT[47]
net (fo=1, routed) 0.000 7.622 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__3/DSP_ALU.ALU_OUT<47>
DSP48E2_X8Y142 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[47]_PCOUT[47])
0.122 7.744 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__3/DSP_OUTPUT_INST/PCOUT[47]
net (fo=1, routed) 0.014 7.758 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__4/PCIN[47]
DSP48E2_X8Y143 DSP_ALU (Prop_DSP_ALU_DSP48E2_PCIN[47]_ALU_OUT[20])
0.546 8.304 f topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__4/DSP_ALU_INST/ALU_OUT[20]
net (fo=1, routed) 0.000 8.304 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__4/DSP_ALU.ALU_OUT<20>
DSP48E2_X8Y143 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[20]_P[20])
0.109 8.413 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__4/DSP_OUTPUT_INST/P[20]
net (fo=2, routed) 0.262 8.675 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__4_n_85
SLICE_X59Y360 LUT3 (Prop_F5LUT_SLICEM_I1_O)
0.117 8.792 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30[63]_i_12__1/O
net (fo=2, routed) 0.193 8.985 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30[63]_i_12__1_n_0
SLICE_X59Y360 LUT4 (Prop_G6LUT_SLICEM_I3_O)
0.090 9.075 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30[63]_i_17__1/O
net (fo=1, routed) 0.016 9.091 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30[63]_i_17__1_n_0
SLICE_X59Y360 CARRY8 (Prop_CARRY8_SLICEM_S[6]_CO[7])
0.117 9.208 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[63]_i_2__1/CO[7]
net (fo=1, routed) 0.026 9.234 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[63]_i_2__1_n_0
SLICE_X59Y361 CARRY8 (Prop_CARRY8_SLICEM_CI_O[0])
0.056 9.290 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[71]_i_2__1/O[0]
net (fo=2, routed) 0.497 9.787 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_14__8[57]
SLICE_X55Y350 LUT6 (Prop_B6LUT_SLICEL_I3_O)
0.051 9.838 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30[63]_i_9__1/O
net (fo=1, routed) 0.009 9.847 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30[63]_i_9__1_n_0
SLICE_X55Y350 CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7])
0.186 10.033 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[63]_i_1__1/CO[7]
net (fo=1, routed) 0.026 10.059 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[63]_i_1__1_n_0
SLICE_X55Y351 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
0.015 10.074 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[71]_i_1__1/CO[7]
net (fo=1, routed) 0.026 10.100 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[71]_i_1__1_n_0
SLICE_X55Y352 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
0.015 10.115 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[79]_i_1__1/CO[7]
net (fo=1, routed) 0.026 10.141 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[79]_i_1__1_n_0
SLICE_X55Y353 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
0.015 10.156 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[87]_i_1__1/CO[7]
net (fo=1, routed) 0.026 10.182 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[87]_i_1__1_n_0
SLICE_X55Y354 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
0.015 10.197 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[95]_i_1__1/CO[7]
net (fo=1, routed) 0.026 10.223 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[95]_i_1__1_n_0
SLICE_X55Y355 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
0.015 10.238 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[103]_i_1__1/CO[7]
net (fo=1, routed) 0.026 10.264 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[103]_i_1__1_n_0
SLICE_X55Y356 CARRY8 (Prop_CARRY8_SLICEL_CI_O[1])
0.076 10.340 r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[106]_i_1__1/O[1]
net (fo=1, routed) 0.025 10.365 topDesign/topMod/tile_2/fpuOpt/dfma/fma/mulAddResult[105]
SLICE_X55Y356 FDRE r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[105]/D
(clock clk_out1_corePLL rise edge)
5.000 5.000 r
E12 0.000 5.000 r sys_clock_p (IN)
net (fo=0) 0.000 5.000 sys_clock_ibufds/I
HPIOBDIFFINBUF_X1Y300
DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
0.433 5.433 r sys_clock_ibufds/DIFFINBUF_INST/O
net (fo=1, routed) 0.040 5.473 sys_clock_ibufds/OUT
E12 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
0.000 5.473 r sys_clock_ibufds/IBUFCTRL_INST/O
net (fo=1, routed) 0.297 5.770 corePLL_clk_in1
BUFGCE_X1Y289 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.024 5.794 r corePLL_clk_in1_BUFG_inst/O
net (fo=20, routed) 0.876 6.670 corePLL/inst/clk_in1
MMCM_X1Y11 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
0.630 7.300 r corePLL/inst/mmcme4_adv_inst/CLKOUT0
net (fo=1, routed) 0.214 7.514 corePLL/inst/clk_out1_corePLL
BUFGCE_X1Y266 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.024 7.538 r corePLL/inst/clkout1_buf/O
X3Y8 (CLOCK_ROOT) net (fo=62108, routed) 2.902 10.440 topDesign/topMod/tile_2/fpuOpt/dfma/fma/clk_out1
SLR Crossing[2->1]
SLICE_X55Y356 FDRE r topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[105]/C
clock pessimism -0.237 10.203
clock uncertainty -0.127 10.076
SLICE_X55Y356 FDRE (Setup_BFF_SLICEL_C_D)
0.025 10.101 topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[105]
required time 10.101
arrival time -10.365
slack -0.263
Slack (VIOLATED) : -0.263ns (required time - arrival time)
Source: topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/sExp_Z_reg[2]/C
(rising edge-triggered cell FDRE clocked by clk_out1_corePLL {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: topDesign/topMod/tile_2/fpuOpt/regfile_reg[16][11]/D
(rising edge-triggered cell FDRE clocked by clk_out1_corePLL {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_out1_corePLL
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (clk_out1_corePLL rise@5.000ns - clk_out1_corePLL rise@0.000ns)
Data Path Delay: 5.024ns (logic 1.322ns (26.314%) route 3.702ns (73.686%))
Logic Levels: 14 (LUT3=2 LUT5=5 LUT6=7)
Clock Path Skew: -0.137ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.189ns = ( 10.189 - 5.000 )
Source Clock Delay (SCD): 5.036ns
Clock Pessimism Removal (CPR): -0.291ns
Clock Uncertainty: 0.127ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.243ns
Phase Error (PE): 0.000ns
Clock Net Delay (Source): 2.957ns (routing 1.411ns, distribution 1.546ns)
Clock Net Delay (Destination): 2.651ns (routing 1.282ns, distribution 1.369ns)
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
(clock clk_out1_corePLL rise edge)
0.000 0.000 r
E12 0.000 0.000 r sys_clock_p (IN)
net (fo=0) 0.000 0.000 sys_clock_ibufds/I
HPIOBDIFFINBUF_X1Y300
DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
0.530 0.530 r sys_clock_ibufds/DIFFINBUF_INST/O
net (fo=1, routed) 0.050 0.580 sys_clock_ibufds/OUT
E12 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
0.000 0.580 r sys_clock_ibufds/IBUFCTRL_INST/O
net (fo=1, routed) 0.335 0.915 corePLL_clk_in1
BUFGCE_X1Y289 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.028 0.943 r corePLL_clk_in1_BUFG_inst/O
net (fo=20, routed) 0.991 1.934 corePLL/inst/clk_in1
MMCM_X1Y11 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
-0.127 1.807 r corePLL/inst/mmcme4_adv_inst/CLKOUT0
net (fo=1, routed) 0.244 2.051 corePLL/inst/clk_out1_corePLL
BUFGCE_X1Y266 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.028 2.079 r corePLL/inst/clkout1_buf/O
X3Y8 (CLOCK_ROOT) net (fo=62108, routed) 2.957 5.036 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/clk_out1
SLR Crossing[2->1]
SLICE_X74Y368 FDRE r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/sExp_Z_reg[2]/C
SLICE_X74Y368 FDRE (Prop_AFF_SLICEM_C_Q)
0.077 5.113 r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/sExp_Z_reg[2]/Q
net (fo=33, routed) 0.592 5.705 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/sExp_Z[2]
SLICE_X81Y350 LUT6 (Prop_F6LUT_SLICEM_I3_O)
0.148 5.853 r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_80__1/O
net (fo=1, routed) 0.086 5.939 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_80__1_n_0
SLICE_X81Y350 LUT5 (Prop_D5LUT_SLICEM_I4_O)
0.066 6.005 r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_54__1/O
net (fo=1, routed) 0.186 6.191 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/roundRawFNToRecFN/roundAnyRawFNToRecFN/p_0_in[17]
SLICE_X81Y350 LUT6 (Prop_H6LUT_SLICEM_I1_O)
0.125 6.316 f topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_26__1/O
net (fo=1, routed) 0.163 6.479 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_26__1_n_0
SLICE_X80Y350 LUT6 (Prop_A6LUT_SLICEM_I3_O)
0.150 6.629 r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_8__1/O
net (fo=6, routed) 0.139 6.768 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/roundRawFNToRecFN/roundAnyRawFNToRecFN/_T_111__24
SLICE_X80Y352 LUT5 (Prop_H5LUT_SLICEM_I3_O)
0.161 6.929 r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[30][0]_i_26__1/O
net (fo=26, routed) 0.314 7.243 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/roundRawFNToRecFN/roundAnyRawFNToRecFN/_T_132__0
SLICE_X79Y350 LUT5 (Prop_F6LUT_SLICEL_I1_O)
0.123 7.366 f topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[30][26]_i_37__1/O
net (fo=6, routed) 0.199 7.565 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[30][26]_i_37__1_n_0
SLICE_X76Y352 LUT6 (Prop_F6LUT_SLICEM_I1_O)
0.037 7.602 r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[30][26]_i_18__1/O
net (fo=7, routed) 0.282 7.884 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[30][26]_i_18__1_n_0
SLICE_X79Y351 LUT6 (Prop_A6LUT_SLICEL_I4_O)
0.035 7.919 f topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_29__1/O
net (fo=1, routed) 0.087 8.006 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_29__1_n_0
SLICE_X79Y352 LUT5 (Prop_B6LUT_SLICEL_I0_O)
0.090 8.096 f topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_9__1/O
net (fo=9, routed) 0.165 8.261 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/reg_fflags[1]_i_9__1_n_0
SLICE_X79Y353 LUT3 (Prop_D5LUT_SLICEL_I0_O)
0.096 8.357 f topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[30][22]_i_20__1/O
net (fo=23, routed) 0.317 8.674 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[30][22]_i_20__1_n_0
SLICE_X79Y344 LUT5 (Prop_B6LUT_SLICEL_I0_O)
0.090 8.764 r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[30][11]_i_7__1/O
net (fo=1, routed) 0.312 9.076 topDesign/topMod/tile_2/fpuOpt/divSqrt_1/divSqrtRecFNToRaw/divSqrt_io_out[11]
SLICE_X71Y340 LUT6 (Prop_F6LUT_SLICEL_I0_O)
0.035 9.111 r topDesign/topMod/tile_2/fpuOpt/divSqrt_1/divSqrtRecFNToRaw/regfile[30][11]_i_3__1/O
net (fo=23, routed) 0.506 9.617 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/sign_Z_reg_0[11]
SLICE_X64Y335 LUT3 (Prop_A6LUT_SLICEM_I2_O)
0.038 9.655 f topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[16][11]_i_2__1/O
net (fo=7, routed) 0.303 9.958 topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[16][11]_i_2__1_n_0
SLICE_X65Y335 LUT6 (Prop_H6LUT_SLICEL_I5_O)
0.051 10.009 r topDesign/topMod/tile_2/fpuOpt/divSqrt/divSqrtRecFNToRaw/regfile[16][11]_i_1__1/O
net (fo=1, routed) 0.051 10.060 topDesign/topMod/tile_2/fpuOpt/divSqrt_n_801
SLICE_X65Y335 FDRE r topDesign/topMod/tile_2/fpuOpt/regfile_reg[16][11]/D
(clock clk_out1_corePLL rise edge)
5.000 5.000 r
E12 0.000 5.000 r sys_clock_p (IN)
net (fo=0) 0.000 5.000 sys_clock_ibufds/I
HPIOBDIFFINBUF_X1Y300
DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
0.433 5.433 r sys_clock_ibufds/DIFFINBUF_INST/O
net (fo=1, routed) 0.040 5.473 sys_clock_ibufds/OUT
E12 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
0.000 5.473 r sys_clock_ibufds/IBUFCTRL_INST/O
net (fo=1, routed) 0.297 5.770 corePLL_clk_in1
BUFGCE_X1Y289 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.024 5.794 r corePLL_clk_in1_BUFG_inst/O
net (fo=20, routed) 0.876 6.670 corePLL/inst/clk_in1
MMCM_X1Y11 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
0.630 7.300 r corePLL/inst/mmcme4_adv_inst/CLKOUT0
net (fo=1, routed) 0.214 7.514 corePLL/inst/clk_out1_corePLL
BUFGCE_X1Y266 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.024 7.538 r corePLL/inst/clkout1_buf/O
X3Y8 (CLOCK_ROOT) net (fo=62108, routed) 2.651 10.189 topDesign/topMod/tile_2/fpuOpt/clk_out1
SLR Crossing[2->1]
SLICE_X65Y335 FDRE r topDesign/topMod/tile_2/fpuOpt/regfile_reg[16][11]/C
clock pessimism -0.291 9.899
clock uncertainty -0.127 9.772
SLICE_X65Y335 FDRE (Setup_HFF_SLICEL_C_D)
0.025 9.797 topDesign/topMod/tile_2/fpuOpt/regfile_reg[16][11]
required time 9.797
arrival time -10.060
slack -0.263
Slack (VIOLATED) : -0.262ns (required time - arrival time)
Source: topDesign/topMod/tile_2/fpuOpt/dfma/in_in2_reg[63]_replica/C
(rising edge-triggered cell FDSE clocked by clk_out1_corePLL {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: topDesign/topMod/tile_2/fpuOpt/dfma/fma/_T_30_reg[67]/D
(rising edge-triggered cell FDRE clocked by clk_out1_corePLL {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_out1_corePLL
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (clk_out1_corePLL rise@5.000ns - clk_out1_corePLL rise@0.000ns)
Data Path Delay: 5.052ns (logic 3.714ns (73.515%) route 1.338ns (26.485%))
Logic Levels: 18 (CARRY8=4 DSP_A_B_DATA=1 DSP_ALU=3 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=3 DSP_PREADD_DATA=1 LUT3=2 LUT4=1 LUT6=1)
Clock Path Skew: -0.109ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.242ns = ( 10.242 - 5.000 )
Source Clock Delay (SCD): 5.115ns
Clock Pessimism Removal (CPR): -0.236ns
Clock Uncertainty: 0.127ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.243ns
Phase Error (PE): 0.000ns
Clock Net Delay (Source): 3.036ns (routing 1.411ns, distribution 1.625ns)
Clock Net Delay (Destination): 2.704ns (routing 1.282ns, distribution 1.422ns)
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
(clock clk_out1_corePLL rise edge)
0.000 0.000 r
E12 0.000 0.000 r sys_clock_p (IN)
net (fo=0) 0.000 0.000 sys_clock_ibufds/I
HPIOBDIFFINBUF_X1Y300
DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
0.530 0.530 r sys_clock_ibufds/DIFFINBUF_INST/O
net (fo=1, routed) 0.050 0.580 sys_clock_ibufds/OUT