VCU118 (+NVDLA) Implementation


#1

Hello guys,

I’ve been implementing Xilinx Ultrascale VCU118 (Sifive core + NVDLA) these days. I cloned the master branch of freedom and compiled using Makefile.vcu118-iofpga-nvdla… the timing is -110ps, but I bypassed the final check and managed to generate the mcs file for the rom.

On the Linux image side, I connected a flashed SDCard via PMOD to VCU118, not the slot on the board.

The question is that as I boot the FPGA from vivado hw server “boot from configuration memory device” or reboot the FPGA, there’s no UART info output but GPIO_LED0 and GPIO_LED1 are flashing (like ~1Hz). I guess the core is running because I saw from U500 guide that an LED blink demo should be running?

Is it because that I should change the scala file at “fpga-shells/src/main/scala/shell/xilinx/VCU118NewShell.scala”? or the “VCU118Shell.scala”? There’s some pcie and ddr code in it. I’m just uncertain about it because generating mcs takes 8 hours…

Hopefully some guys here could help me with this issue. Thanks a lot!


(Wesley W. Terpstra) #2

That design expects PCIe adapters on both the FMC+ and edge connector. If you don’t have those adapters to provide a PCIe reference clock, it won’t come out of reset. The blink pattern you describe (1Hz alternating) indicates that the board did not come out of reset.

Try commenting out these two lines:
val fmc = Overlay(PCIeOverlayKey) (new PCIeVCU118FMCOverlay (_, _, ))
val edge = Overlay(PCIeOverlayKey) (new PCIeVCU118EdgeOverlay (
, _, _))
in VCU118NewShell.scala. Then the design will not add PCIe and wait for the clocks.

As for missing timing by 110ps, that should be ok. Are you using vivado 2018.2? That’s the only one we support on that board.


#3

Thanks, Mr. Terpstra!

Yeah I commented the fmc and edge. But I also commented the val pcie… Then I boot the board and the leds still keep flashing. Maybe it is because I should not comment the val pcie… I’ll make another try later.

Yes I’m using Vivado 2018.2.

I checked the generated design and saw that the there’s only Chiplink IO constraints on the board. Then I got this question: Is the iofpga-nvdla config designed to use VCU118 as a peripheral device for Hifive Unleashed? Or this config contains RISC-V core and NVDLA design in VU9P together? Because I saw another u500devkit config and guessed that it maybe a single RISC-V core – then is it possible to boot a standalone RISCV + nvdla environment on VCU118 only? I’m just a little bit puzzled about the make configs in the repo…


(Wesley W. Terpstra) #4

The iofpga design definitely expects to find a HiFive Unleashed attached to the FMC connector. If it is not there, you won’t have any processors and it won’t come out of reset!


(Wesley W. Terpstra) #5

One could make an NVDLA + soft-cpu RISC-V SoC, but AFAIK no one has done this so far.


#6

Thanks for you reply! Now I’ve fully understood this config now.