Linux does not boot with U500 on VC707

I am able to build the u500vc707devkit mcs file and program the VC707 linear flash, and follow the sw development flow to build bbl.bin and put that on an SD card. With SD card in and SW11 set to “11010” on VC707, Linux does not boot on power up - actually nothing comes out on the uart port. The format on the SD card is FAT32, and there are no other peripherals connected to the VC707. I cloned from the sifive git repo today.

Any suggestions on what I might have overlooked and to try? Thanks.

Do you have a HiTechGlobal PCIe FMC card attached to your VC707 board ?
At present, the FMC module supplies the main clock to the coreplex and without it the system will not boot.


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The filesystem on the SD card must be a raw image as produced by the freedom-u-sdk. However, you would still see something on the UART even with a bad SD card image, so I assume Henry is right and your problem is a missing clock.

Thanks for the quick response. No, I don’t have a PCIe FMC card attached. Is there a clock source on the VC707 I can use to provide this clock instead? I would like to run the VC707 standalone if possible.

You will have to change the RTL, but yes, you could use the VC707’s onboard oscillator instead of the PCIe clock. Of course, PCIe will no longer work then.

Greetings. I’m trying to boot Linux with U500 on VC707 card, with no success. I have performed all steps described in The HTG X8 PCI Express root card was attached and configured, VC707 boot mode set (SW11 to ‘11010’) and FPGA programed with bitstreams. I built bbl.bin image and transferred it to sdcard using dd, as described.
I have connected PC to VC707 J17 UART using USB cable, and Windows detects it as Silicon Labs CP210x USB to UART Bridge and assigns COM2 port. After powering up the VC707, Linux does not boot – I can’t see anything in terminal attached to this port.
Do you have any idea what may be the problem?

Have you used your com port for anything else before? Did you have it set to 115200 8n1?
I would expect it to at least print out INIT when you power it on.

Also can you confirm that the FPGA is configuring - is the DONE LED lit on the VC707 ?

The port is set correctly, 115200, 8 bits, 1 stop bit, parity None. I have tried with different terminal programs and on two different computers, as well. The result is the same.

When the board is powered up, after short time DONE, INIT and four leds below are lit.

I have succeeded to boot Linux. The problem was with X8 PCI Express Gen1/2/3 FMC Module, more precisely with power switch S2. Getting started guide (section 2.2, page 4) states “set the power switch on the FMC module towards the VC707, this sets the FMC to be powered by the VC707”, but it seems that switch on my FMC module has different orientation.


I have a similar problem and behavior as engll (no uart output when the FMC1 connector for PCIe is unconnected).
My question is if terpstra suggestion corresponds to changing the PCIe 100MHz refclk source.
So instead of getting as PCIe refclk input clock from the FMC1, should I get it from another source?

In fpga-shells/src/main/scala/shell/xilinx/VC707NewShell.scala, comment out line 213:
val pcie = Overlay(PCIeOverlayKey) (new PCIeVC707Overlay (_, _, _))

Then it will work without PCIe.

Thanks for your quick reply. Unfortunately I still encounter the same problem (no-uart output). Also I just noticed that this thread concerns the “u500vc707devkit” build, whereas in my case my build concerns the “vc707-iofpga”. I am actually (maybe I should have give this piece of information earlier) trying to port the vc707-iofpga to another XIlinx board (KCU105). Photo of the setup: I have made a port of the the original “vc707-iofpga” build and another one using your scala modification (val pcie = …). My latest findings in the ported design without the pcie enabled are: (i) leds[1:0] are toggleing, led[4] is always ON and the rest of the leds are OFF (rest of leds: led[7:5]=0, led[3:2]=0) (ii) rxPLL is not locked and its reset is 0 (iii) the core_reset signal is “1” (generated sifive.freedom.unleashed.IOFPGAConfig_With200MHz.v file). I have cross-checked the FMC Pins and everything seems OK. The corePLL locks OK. Also the DDR4 MIG controller works OK (calibration passes). The top-level ereset_n pin is 1. Also the power good signal from the unleashed board (name: PG_M2C FMC pin: F1) is activated (equals to “1”).
Any further information would be appreciated.

Let me give more information about my setup.

HW srcs:

  1. I have compiled the freedom repository using the vc707-iofpga build (run first “make -f Makefile.vc707-iofpga verilog” then run “make -f Makefile.vc707-iofpga mcs”).
  2. Modified the generated vivado (ver.16.4) project to match the KCU105 board (modified the generated verilog file in order to replace the DRAM controller and modify the constraint to match the corresponding pins of chiplink, DRAM, system clock, leds, buttons e.t.c.).
  3. Generate bitstream.

Create the sd-card image for the unleashed board, following the instructions of unleashed getting started PDF.

Check if the unleashed board works OK without the connection with the KCU105 fpga board:
Insert the card to the unleashed board and power-ON the unleashed board alone. Board boots OK.

Putting it all together:

  1. Plug the unleashed board to the FMC of the KCU105 board and make sure the ext. 12v power supply is disconnected. Power switch of the unleashed Board is OFF.
  2. Power-on the KCU105 board and download the bitstream through jtag.
  3. Turn ON the power switch on the SIfive unleashed board.
  4. No uart output. Also checked the alternative uart output (the one from GPIO pins: UART0_TX, UART0_RX 1.8volt), again no-output.

Chipscope debug (as mentioned in my previous reply and some additional info): corePLL is locked, rxPLL is unlocked, ereset_n is high, rxPLL reset is low, power good of the unleashed board is high (fpga input from the PG_M2C FMC pin), chiplink tx clock from the fpga to the unleashed board is OK. Conclusion so far: the output lock signal of rxPLL is low which means that the incoming rx clock from the unleashed board to the fpga is dead.
fpga board leds: led[1:0] are toggleing, the led[4] is always ON

I have repeated the previous steps also using as baseline HW design the VCU118 (vivado 18.2), again the same results.

Further info (terminal output when the unleashed board is not connected to the KCU105 fpga board):
SiFive FSBL: 2018-03-20
HiFive-U serial #: 0000017a

Build commit hashes:
freedom: 808ec8db4f9…
freedom-u-sdk: 1dfb584c07…

Hi Guys,

After almost 3 weeks of debugging I finally managed to make the unleashed board boot using the KCU105 board!
Let me tell you the root of the problem.
The KCU105 board embeds 2 fpgas. The main (Kintex) fpga and a very small zynq fpga which acts as system controller for the kintex development board (configuration of clocks, voltages e.t.c.).
When the unleashed board is being attached to the FMC, the zynq controller makes reads to the i2c bus (address 0x12) in order to setup the VADJ1V8 voltage. The correct voltage value should be 1.8v, however the zynq controller reads a value which equals to 0.3v instead of 1.8v and sets the VADJ1V8 source at 0.3v.
By over-writting the value of VADJ1V8 to 1.8v through the zynq-controller menu (uart), the unleashed board finally booted! Even though I had written the VADJ1V8 to 1.8v before connecting the unleashed board to the FMC, after plugging it, the value was re-written wrong due to the i2c polling configuration (as mentioned before).
So I guess the “bug” happens to be at the i2c slave of the unleashed board. The zynq controller reads wrong value for the VADJ1V8 voltage at the i2c address “0x12”. Looking at the unleashed schematics, the component “U49” at page 8 seems to feed the zynq i2c read request.

I don’t think that EEPROM on the HiFive Unleashed is programmed.

It seems that the EEPROM contains zero values (I do know if it is an EEPROM by the way, the schematics do not show any details, there is a “U49” component at page 8 of the schematics). I confirmed this by reading all the i2c addresses from the small zynq controller of KCU105 dev board.
According to the XIlinx Dev Board Guide (ug917 pg. 80), the KCU105 implements the ANSI/VITA 57.1 (section 5.5.1 IPMI support) functionality.
So it seems that the sifive unleashed board provides wrong values through the i2c bus, and apparently it is NOT fully compliant with the VITA 57.1 FMC standard.