Attempt to add kc705 firmware based on vc707 code


(ZhuXuanlong) #1

Hi,
I tried to add kc705 firmware on freedom based on vc707 code. But in the process of compiling mcs, there are the following errors. Please help to analyze the possible reasons. Thank you very much!

ERROR: [Synth 8-448] named port connection ‘sys_clk_i’ does not exist for instance ‘blackbox’ of module ‘kc705mig1gb’ [/share/freedom/builds/kc705-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:362356]
WARNING: [Synth 8-350] instance ‘blackbox’ of module ‘kc705mig1gb’ requires 67 connections, but only 65 given [/share/freedom/builds/kc705-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:362305]
ERROR: [Synth 8-6156] failed synthesizing module ‘XilinxKC705MIGIsland’ [/share/freedom/builds/kc705-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:361397]
ERROR: [Synth 8-6156] failed synthesizing module ‘XilinxKC705MIG’ [/share/freedom/builds/kc705-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:366117]
ERROR: [Synth 8-6156] failed synthesizing module ‘DevKitFPGADesign’ [/share/freedom/builds/kc705-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:430158]
ERROR: [Synth 8-6156] failed synthesizing module ‘DevKitWrapper’ [/share/freedom/builds/kc705-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:435457]
ERROR: [Synth 8-6156] failed synthesizing module ‘KC705Shell’ [/share/freedom/builds/kc705-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:435683]

Finished RTL Elaboration : Time (s): cpu = 00:03:59 ; elapsed = 00:04:25 . Memory (MB): peak = 2586.137 ; gain = 1039.297 ; free physical = 3337 ; free virtual = 7992

RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
292 Infos, 415 Warnings, 0 Critical Warnings and 7 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

while executing

“source [file join $scriptdir “synth.tcl”]”
(file “/share/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl” line 13)
INFO: [Common 17-206] Exiting Vivado at Fri Aug 16 14:14:26 2019…
common.mk:81: recipe for target ‘/share/freedom/builds/kc705-u500devkit/obj/KC705Shell.bit’ failed
make: *** [/share/freedom/builds/kc705-u500devkit/obj/KC705Shell.bit] Error 1


(ZhuXuanlong) #2

The reason is that in the Mig project configuration, System Clock is assigned “Differential”, which should be matched “No Buffer”.