PLL Generation at 384MHz Causes Strange Behavior

Hello Team,

I’ve hand written an initial port of my operating system (Harvest) to the HiFive1 board. All it does is boot to a console, but it’s working. I am curious about one issue, however, the PLL. I had to sneak a look at the BSP source to identify what I was doing wrong but apparently I was using a PLL_F value that is too high, but I’m not sure why?

My PLLCFG is {r=1, f=47, q=1} for, presumably, a 384MHz clock. When I use this configuration and not the one used in the BSP {1, 31, 1} I get strange behavior. JTAG fails and the board can’t read from SPI nor RAM and traps at 0x0. Recovery means a reset and initializing JTAG during BSP’s “green delay”.

Why does 256MHz clock work but 384 does not?

Thank you and happy new year!

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We only test/guarantee the boards up to 320MHz plus some margin. Depending on fabrication variance, some parts might run considerably faster or not much faster at all.

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Ahh, ok. Thanks for the clarification, Krste. That makes sense.