I am having difficulty finding the coreclk frequency at powerup. I see on the schematic that there is an external 16 MHz crystal.
Then looking at Chapter 6 (Clock Genration) it seems that the default PLL values are pllr=1, pllf=31, and pllq=3 giving effective values of R=2, F=64, and Q=8. So pllout = 16 / 2 * 64 / 8 = 64 MHz. Not very fast andn below the required minimum. I am missing something. The plloutdiv defaults to 0, so does not affect anything.
My reading of the diagram in section 6.1 is that pllout becomes coreclk. So the default powerup coreclk is only 64 MHz? Am I reading this correctly? How do I get the advertised 320 Mhz? It would seem I need pllf=39 and pllq=1. But there also is some limitiation on the SPI0 clock frequency for the Flash memory. Can I juggle both of these to raise the tlclk while keeping the Flash happy?
The reason I am checking this is that I need to set an SPI1 bit-clock rate very carefully for my application and need to know exactly what tlclk is.
On further reading I see that actually the PLL is bypassed at reset and theprogrammable oscillator is in control, running at 18.8 MHz plus or minus 50%!