The FE310-G002 manual is not real clear about this and I discovered it by experiment. On page 30 it talks about the PLLBYPASS flag bit, which not only bypasses the PLL, it powers it down. The text states that the PLL can be reconfigured in this state in the PLLCFG register, which is true. It also says that the PLL should not be used until it has acheived lock.
What it does not come right out and say is that, until you clear the PLLBYPASS bit, the PLL will never acheive lock because it is powered down! So the reliable sequence is,
- Clear the PLLSEL bit, which makes the CPU use the Ring oscillator as the clock. For me this turns out to be 20.2 MHz with the default settings but your mileage may vary. The Ring oscillator is not very precise so don’t run this way for long.
- Now you can set PLLBYPASS which powers down the PLL.
- Change the PLL R, F, and Q factors as desired, see pages 29 and 30.
- Clear PLLBYPASS. This starts up the PLL again and it will try to acheive lock.
- Wait at least 100 microseconds for the lock indicator to become stable. I use 4 ticks of the 32 KHz low-frequency timer for this.
- Wait for the PLLLOCKED bit to turn on. This is the high-order bit in the PLLCFG register.
- Finally set the PLLSEL bit to switch the CPU from using the Ring oscillator to the PLL output.
At this point you will probably need to change the clock dividers for UARTs and SPI devices to account for the new central clock frequency.