I am trying to build a Freedom U500, without the PCIe interface instead replace it with Ethernet interface.
To begin with, i downloaded the repo from github and went through the current implementation and fpga scripts.
I could not figure out the exact point where PCIe was getting interfaced to PLIC and L2 Cache.
Any pointer would be helpful here.
Also, i do not have a vc707 dev board with me. I have a custom v2000T device.
I aim to port U500 design to v2000T. Let me know if this would be possible.
It’s in sifive-blocks/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala:11-15. If you remove the PCIe port, it will complain that there is no longer a bus master for the periphery l2 crossbar. So you will need to put some dummy bus master there instead.
Porting the design to another FPGA is of course possible, but will not be trivial.
The U500 Dev Kit is beyond my budget, so I have also considered porting to a Lattice FPGA board. Could you please post any progress you might make in your porting efforts? I will do the same, if I make any -
Under GitHub sifive/sifive-blocks “Common RTL blocks used in SiFive’s projects” I can only find device entries for the vc707. Are those blocks common to the Arty device as well?
The sifive-blocks repo is used for both devices, but the MIG and PCIe devices there are specifically for the vc707. If you want to port the U500 to the arty, the MIG at least will need to be generalised to support both the DDR width of the arty and the vc707.
Thank You for the quick reply, I was able to port the MIG for v2000T.
I am trying to write a dummy master based on TLInput/TLOutput, will post once i complete.
Next step would be to configure linux to look for boot loader and kernel within the DDR3 address space.
Will get back once i reach that step.
yes, I connected uart I/O ports to AU33 and AU36 of VC709, but nothing printed on the screen. Meanwhile I caught signals of uart module by Debug, and it showed that the print command had sent to uart module，but the uart_tx was always high.I still trying to find the reason.
Two thoughts. First, did you perhaps mix up RX/TX? This happens to me all the time. Second, did you set a reasonable value into the clock divider register?
Yes, the HiTechGlobal X8 PCI Express Gen 1/2/3 FMC Module cannot be used with VC709.
Basically the transceiver pins which are wired to the FMC do not connect to the hard gen 3 PCIe block in the FPGA :
Table 4-10 in [0] shows the VC690 in FF1761 has 3 PCIe blocks with PCIe lane 0 at transceivers X1Y11, X1Y23, X1Y35.
Of these, the VC709 only connects X1Y35 to the FMC (see Table 1-9 in [1]) on FMC1 HPC DP7
This FMC pin is not connected to PCIe lane 0 on the HiTech FMC module
I’ve already known the reason why uart module couldn’t work now. As I was not familiar with how to use uart model of sifive, I didn’t try to send enable signal to uart txctrl reg. Thanks for all your replays before.
but now the problem is that it just print icon of sifive after the bootloader copy bbl.bin fom flash to DDR. Do you know the most likely reasons of this?
I understand the reason you said that why the HiTechGlobal X8 PCI Express Gen 1/2/3 FMC Module cannot be used with VC709. Thanks for your replays.
However I saw the passage in page 239 said : “IMPORTANT: These configurations are recommended; however, other configurations might work aswell as long as timing is met. Constraints for the recommended pinouts are generated by the tool. Foralternate pinouts, you can manually modify the generated constraints in the XDC file.” Regarding to that, is that means it’s unnecessarily to use the configurations in Table 4-10? Furthermore, the user_link_up which is caught by Debugger after VC709 powered on stays high.What about your idea？
I have known the reason why it just print the icon of sifive. The DDR of VC709 is 4GB and the width of ddr3_addr is 16 bits, but the DDR of VC707 is 1GB and the width of ddr3_addr is 14 bits. And I just replace the mig but forget widen the ddr3_addr of top module.
Thanks for all your replays again.
