I am trying to build a Freedom U500, without the PCIe interface instead replace it with Ethernet interface.
To begin with, i downloaded the repo from github and went through the current implementation and fpga scripts.
I could not figure out the exact point where PCIe was getting interfaced to PLIC and L2 Cache.
Any pointer would be helpful here.
Also, i do not have a vc707 dev board with me. I have a custom v2000T device.
I aim to port U500 design to v2000T. Let me know if this would be possible.