Custom U500 Linux SDK build on Fedora Core 23

Archive Freedom U500
1

Hi.
I have Xilinx Artix-7 35T Arty FPGA Evaluation board and Vivaldo 2016.2
I have successfully uploaded and run Your bitstream freedom-u500-arty-0-1.mcs

I have successfully clone and build on FC23 Linux U500 SDK (work/bbl.bin)
In Write Memory Configuration File Dialog of Vivaldo 2016.2 (Windows 7) I do:

write_cfgmem -format mcs -size 16 -interface SPIx4 -loadbit "up 0x00000000 C:/Temp/riscv/freedom-u500-arty-0-1.bit " -loaddata "up 0x00400000 C:/Temp/riscv/bbl.bin " -force -file "C:/Temp/riscv/freedom-u500-arty-custom.mcs"
Creating config memory files…
Creating bitstream load up from address 0x00000000
Loading bitfile C:/Temp/riscv/freedom-u500-arty-0-1.bit
Creating bitstream load up from address 0x00400000
Loading datafile C:/Temp/riscv/bbl.bin
Writing file C:/Temp/riscv/freedom-u500-arty-custom.mcs
Writing log file C:/Temp/riscv/freedom-u500-arty-custom.prm
===================================
Configuration Memory information
===================================
File Format MCS
Interface SPIX4
Size 16M
Start Address 0x00000000
End Address 0x00FFFFFF

Addr1 Addr2 Date File(s)
0x00000000 0x0021728B Aug 18 00:08:12 2016 C:/Temp/riscv/freedom-u500-arty-0-1.bit
0x00400000 0x00A7F687 Aug 17 00:26:12 2016 C:/Temp/riscv/bbl.bin
write_cfgmem: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 929.855 ; gain = 86.027

After that in Program Configuration Memory Device Dialog I do:

set_property PROGRAM.ADDRESS_RANGE {entire_device} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.FILES [list “C:/Temp/riscv/freedom-u500-arty-custom.mcs” ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]]
set_property PROGRAM.PRM_FILE {C:/Temp/riscv/freedom-u500-arty-custom.prm} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-up} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
_startgroup _
_if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] } { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; }; _
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
Mfg ID : 20 Memory Type : ba Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0
Performing Erase Operation…
Erase Operation successful.
Performing Program and Verify Operations…
Program/Verify Operation successful.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:07 ; elapsed = 00:04:06 . Memory (MB): peak = 929.855 ; gain = 0.000
endgroup

Then I run putty on COM4 speed 112500 and Boot from Configuration Memory Device. On serial console has been printed “SiFive RISC-V Coreplex” LOGO and nothing more…
What could I do wrong?

With best Regards, Youry

2

I extract bbl.bin from original freedom-u500-arty-0-1.mcs file, and then repack freedom-u500-arty-custom.mcs with freedom-u500-arty-0-1.bit. Result: my device boot fine…
So, by default in FC23 I make wrong bbl.bin from sources U500 SDK :frowning:

3

Youry, glad to hear your problem appears fixed. Please keep up updated on any progress or issues!!

5

Conclusion: The most recent commits of U500 Linux SDK do broken of image bll.bin (kernel and bootloader hangs on boot, may be outdated bitstream…) for 35T Arty FPGA board.
I do not want to look for errors. For me worked solution is a modified git clone operation:

git clone https://github.com/sifive/freedom-u-sdk.git
cd freedom-u-sdk
git reset --hard 2d533f13f2373b657885834b812fd02253a5f1db
git submodule update --init --recursive
make

Checked on FC23 and Ubuntu 14.04

6

Sorry for causing you additional work and debug. We didn’t properly tag the software version needed for the existing bitstream. Going forward, this will be fixed and we will properly tag the software versions and corresponding bitstreams.

7

hello,I encounter the same situation that boot loader works right but Linux does nothing.I try a lot ,it is still bad.
Until now ,I find that I donot have freedom-u500-arty-0-1.bit.Could you tell me where I can download this file?
thanks a lot by a Chinese student

8

You can download the bit file here: https://dev.sifive.com/develop/freedom-u500-arty-fpga-dev-kit/

9

When I try to access the above link, I am getting “not found”. Has the freedom-u500-arty fpga-dev-kit been abandoned, or is there a problem with the link?

10

https://dev.sifive.com/develop/freedom-u500-vc707-fpga-dev-kit/ works for me. I think the arty turned into fpga.

11

Ahh. I see. There is no more arty version of the U500. Sadly it is only for the VC707 at this time.

We may port the U500 back to the arty, but AFAIK this is not on the schedule yet. The point of the U500 dev design was to help people with PCIe bringup, which the arty cannot do.

12

OK, makes sense. Actually, I bought the Arty because the SiFive Development Kit main page (still) indicates that it could be used for both E300 and E500. Maybe someone should correct that.

I do have a LatticeECP3 Versa Evaluation Board for FPGA which does have PCIe. Any chance of getting the E500 running on that?

13

Thanks, we’ve updated the webpage.

It is possible to port the U500 on different FPGAs, but to keep things simple I believe our plan is to only support the arty and vc707 FPGAs for the time being. If you want to port the U500 to a different FPGA, that would be great and might benefit other riscv-enthusiasts. However, at SiFive we have to pick where to spend our time. I hope you agree it’s best spent on improving the ASICs. :slight_smile:

14

Of course.

You might want to look at this thread as well, in light of the above. It was confusing for me.

Arty U500 Priv 1.9.1 bitstream
Freedom U500

Hi SiFive team,

Could you please post an Arty U500 bitstream that supports Privileged Spec 1.9.1?

Thanks,
AruncreatedNov 11last replyNov 161reply136views2usersmwachs5Megan A. WachsVerified SiFive AccountNov 16Yes,
we are working on updating all the Dev Kits to the latest specs and
will post here when they are ready. Look for these coming in the next
few weeks.

15

Sorry for the confusion. I’ll go reply to the other thread.

16

For build current freedom-u-sdk in FC27 (perl522+) need put this patch with name for example 0002-perl522+.patch in directory freedom-u-sdk/buildroot/package/automake/

diff -Nurp automake-1.15-old/bin/automake.in automake-1.15/bin/automake.in
--- automake-1.15-old/bin/automake.in	2015-01-05 22:25:55.000000001 +0300
+++ automake-1.15/bin/automake.in	2018-03-04 02:59:01.098353979 +0300
@@ -3878,7 +3878,7 @@ sub substitute_ac_subst_variables_worker
sub substitute_ac_subst_variables
{
   my ($text) = @_;
-  $text =~ s/\${([^ \t=:+{}]+)}/substitute_ac_subst_variables_worker ($1)/ge;
+  $text =~ s/\$\{([^ \t=:+{}]+)\}/substitute_ac_subst_variables_worker ($1)/ge;
   return $text;
 }
17

AFAICT this patch does nothing.

18

But without this simple patch on FC27 don’t build subpackage libtirpc from freedom-u-sdk package buildroot

19

Your patch does not actually change the line in question.

20

Sorry, now is correct…

21

hi the u500 do not support artix-7 now only support VC707

do you still have the bitsteam of U500 on artix-7 35T?

could send one to me ?xiaoming1919@foxmail.com
thank you very much