When I try to disable cache, I am not found any instruction can disable/enable cache, also there is no cache invalidate instruction.
Is the cache always on in freedom/rocket implement?
By the way, when generate verilog in rocket, there is “C” attribute, what’s that mean? is it means support cacheable or atomic? if it means cacheable, is it both for instruction and data?
Generated Address Map
0 - 1000 RWX debug-controller@0
3000 - 4000 RW C error-device@3000
10000 - 20000 R X rom@10000
2000000 - 2010000 RW clint@2000000
c000000 - 10000000 RW interrupt-controller@c000000
60000000 - 80000000 RWX mmio@60000000
80000000 - c0000000 RWXC memory@80000000