Two Rocket Based Questions targetting FPGA

Hi SiFive,

Not sure if this is the right venue for these kind of questions, so if it not please direct me to where I should go. I’m presently trying to accomplish two things that will later be joined, but I want to do both individually first for my own understanding.

The First one I’ve already asked in the RISC-V HW Group. Essentially, I’m curious if anyone has built a 32 bit rocket and mapped it to an FPGA and got things running on it. I think I’m relatively close but miss a few connecting points.

The second question is how can I use the Rocket-chip tools to push out a verilog source of only the Rocket-Tile itself, none of the networks or lower level caches included.

If I need to make any clarifications, or if there is a better place to ask, please let me know.

Thank you,
John

John,

I’m curious if anyone has built a 32 bit rocket and mapped it to an FPGA and got things running on it.

The SiFive Freedom (https://github.com/sifive/freedom) repository enables you to build a 32-bit RISC-V core (based on rocket-chip) and put it on a Digilent Arty Development Board. The image in the repository includes other things like UART, GPIO peripherals which allow you do do interesting things with the RISC-V Core. With tweaks to the constraints files you could adjust it to target other FPGA boards.

You can use the Freedom E SDK to get software running on this platform, there are instructions here:

how can I use the Rocket-chip tools to push out a verilog source of only the Rocket-Tile itself, none of the networks or lower level caches included.

The Rocket Tile is part of the hierarchy when you build rocket-chip (or the freedom repo), so you can simply use the Tile as your top level. The codebase isn’t set up to ONLY generate the Tile, but that doesn’t mean you need to use the ExampleTop as your top level.

Thank you, Megan!

That looks hopeful, so I’ll be giving that a run.

Hi again,

Is there any documentation on how to change what is targetted as the top level module? I’ve been looking around, and I can’t figure out how to set the configurations so that the resultant verilog would be only the rocket tile rather than the whole SoC. I’m not trying to push the tile alone to an FPGA.

Thanks

As I said before, if you just build the full thing, you can certainly just pull out the verilog module that you want from the generated verilog, and do whatever with that top module. Rocket-Chip repo isn’t really set up to do what you are asking to do. What is your actual goal, if not putting a Tile onto the FPGA?

Sorry for my misunderstanding on that; I got a little confused.

I was maybe a little unclear. The whole of the work will be on FPGA at some point, but it’ll have different things with the tile, maybe in a manner like the lowRISC untethered work, granted, they did leave much of it intact.