What is open source and what is not?

Archive RISC-V
1

Hi,

I found out about SiFive yesterday and I am super excited about what you are doing. I am aware that RISC-V ISA is open source under the BSD license, and I am curious whether the Coreplex IP will also be released under the BSD or any other open source license.

Thanks!

2

Thanks for your interest in SiFive!

The Rocket Chip Generator is already open sourced here:

Take a look and good luck!

3

Thanks! Do you also plan to publish hardware designs for the Freedom U500 and E300 platforms?

I would really like if you could clarify what exactly is open and what is proprietary.

4

Yes, we are working on preparing and cleaning up the platform code so that we can open source what we can. As we have previously noted, there are still some 3rd party components that we will not be able to open source. Stay tuned for more details, we plan to get this out soon! Thanks for your patience

5

Will do. Thanks!

6

Is E300 platform will have some closed source ?
Cos we are wondering is there will be completely free and open Iot little core (like ARM® Cortex®-M3 -M4),
for next arduino like board ?

7

Any news?

8

Jack, I would really appreciate the answer here.

There were other architectures which I will not name and which were misadvertised as being open, even though they clearly are not. Since everybody likes open source stuff so much these days, this “we are open” kind of advertising tends to work well.

I am aware that openness is one of the key selling points and that you don’t want to break this nice bubble for people that are optimistic about SiFive’s opennes, but the divide between open and closed parts should be made clear. Even “we have not fully decided yet, but we know for certain that X is going to be open and Y is going to be closed” is fine.

9

Is there any plan to publish the sources for the development board FGPA’s?
I would specially be interested in the sources for the arty examples of U500 and E300.

Can you may give me some numbers how many FPGA ressources (slices, memory, etc.) are used for the current examples?

best regards,
Marco

10

I apologize for the delay in responding to everybody, especially to you, Vedran.

We have been extremely busy getting things ready. As you know, what we plan to be open is not just the coreplex, but other important elements that compose the SoC. For example, right now we can say that the interrupt controller, debug, and SoC fabric will be open.

Many of the items we are working on, like the TileLink bus fabric, which we hope will be adopted broadly, are already open-sourced. Even though it’s not complete yet, the work in progress can be seen as part of Rocket-chip at https://github.com/ucb-bar/rocket-chip

We still need to complete a lot of the design work. In addition, as you can imagine, it’s a little bit confusing for other items like the bus fabric to be within the rocket-chip repository, which has historically been more focused on just the CPU.

We are working very hard at enabling a new open source repository that will be much easier to understand the various components. We expect to have this by early to mid October.

11

Thanks for the clarification.

12

To update this thread, the Chisel/RTL code and FPGA compilation flows for both Freedom E300 and U500 are now open source! Check out http://github.com/sifive/freedom to start tinkering.

Have fun!
Megan

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