It’s quite simple to generate RISC-V Verilog with rocket-chip repository, especially if you have an existing FPGA system and are willing to code up the top level wrapper code to interface to the rest of your system.
You can follow the instructions on the rocket-chip README to check out the repository and generate verilog for RocketChipTop.
You will need to choose or create a ‘Config’ which has your exact parameters (number of AXI memory ports, processor size, cache parameters, for example). The README has some information on this, you can browse the Config.scala files to see what sorts of tuning is available, but you can see how close “DefaultConfig”, “TinyConfig”, or “DefaultFPGASmallConfig” is for your purposes.
The DebugModule described in Tim Newsome’s spec is included by default. If you want to add the JTAG interface described in the spec, you can add WithJtagDTM_ to your Config name. So you could build the verilog with something like:
make verilog CONFIG=WithJtagDTM_TinyConfig
Good luck and let us know if you have more questions.