I am trying to test a variant of RocketChip and currently I am trying to understand the provided Scala codes.
However I have few questions concerning the memory and the bootloader. To test the generated verilog I am using an Altera DE2-115 FPGA.
Comparing to the E300ArtyDevKitTop verilog output the rocket chip verilog output shows clear separation for srams from the rest of modules. Which is the wanted outcome, since in altera FPGA the srams are generated separately using memory IPs. Since the E300ArtyDevKitTop verilog procedure is a complete verilog with all the peripherals, I am using it to learn the details of the implementation but I can’t tell the srams module apart. doesn’t the Arty FPGA need an IP module for the srams ?
for E300ArtyDevKitTop bootrom (e300artydevkit.img), is it the compilation of freedom/bootrom/xip/xip.S ?
if so, a linker is not needed here ?
if not, is it possible to have the source code ? Then what’s the use of xip.S ?
and is jumping to 0x20000000 its only functionality ?
For Rocket Chip there is bootrom.S and linker.ld can I use them instead of e300artydevkit.img if I could possibly add the jumping to spi flash address ?
- Is a startup code necessary while compiling C codes to download and run on either Arty FPGA or HiFive board or the bootloader can replace it ?