The load-reserved and store-conditional instructions are only supported on cached regions


(chengpeng0723) #1

There is one sentence which located on page 24 of [SiFive FU540-C000 Manual v1p0]:
The load-reserved and store-conditional instructions are only supported on cached regions,
hence generate an access exception on DTIM and other uncached memory regions.

And also we can see the DDR region are not cacheable in the memory map.
So, does this mean you can not LR/SC an address in the DDR .data sections?
I know I may misunderstand it, please tell me how! Thanks!


(Jim Wilson) #2

The DDR memory region is cacheable. That looks like a typo in the docs. Compare against the U54 Core Complex manual for instance which lists this memory region as cacheable.


(chengpeng0723) #3

Thanks, Jim.