AMO support on the S7 core

HiFive Unmatched
1

I would like to learn more about AMO support on the S7 core in U740. I’m reading the FU740-C000 Manual v1p2, and in Section 3.6, Atomic Memory Operations, it says:

The S7 core supports the RISC‑V standard Atomic (A) extension on the internal memory
regions.

The load-reserved (LR) and store-conditional (SC) instructions are special atomic instructions
that are only supported in data cacheable regions. As the S7 core does not have a data cache,
the LR and SC instructions will always generate a precise access exception.

However it’s not clear what happens for the S7 core to execute an AMO in various memory regions. I was also not able to find the precise definition for ‘internal memory regions’.

For example, would it not be possible to implement a spinlock that works across S7 and U74 cores (at least the ‘normal’ amoswap way), because the S7 core does not have AMO access to any shared main memory?

Thanks for any guidance.

2

Just a… horrible idea, maybe it’s possible to exploit the fact that the S7 does not have a D-cache to sort of ‘emulate’ atomics.