Atomic operations?


Does the HiFive Unleashed board support atomic operations?

(Bruce Hoult) #2

The CPU on the HiFive1 supports the atomic instructions.

As there is only one CPU, no cache, no DMA, no off-chip bus that support is relatively trivial :slight_smile:

I can’t immediately find anything in the E3 Core, E300 platform, or FE310 SoC manuals specifying the exact interaction of interrupts with atomic instructions.

I’m going to make a wild guess that an atomic RMW instruction will be completed before an interrupt is taken. The RISC-V specification requires that a return from interrupt will clear the reservation from a Load-Reserved.


Sorry - I’ve mixed up my boards.

I should have posted this question (and the other) in the HiFive Unleashed sub-forum.

(Bruce Hoult) #4

So, yes, the Hifive Unleashed supports atomic operations and the various processor caches and RAM are fully coherent via the mechanisms in the TileLink interfaces.



I’m interested as I maintain a platform-independent library of lock-free data structures (liblfds).

I want to get hold of an Unleashed as a dev board, to support the platform.